MAC7200 datasheet(842/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

764

Freescale Semiconductor

33.11.3.7 Result Adjustment

The analog conversion circuit delivers a so called raw conversion result determined by the RSD-algorithm.

To increase the accuracy the difference between an ideal transfer curve and the real transfer curve is

minimized. This is done with this block. The adjustment is called multiply-and-add (MADD).

33.11.3.8 Conversion Control

The conversion control block takes care that each conversion is executed in the way specified in the

conversion command word. It controls the analog conversion circuit which will have an influence to the

delivered result.

33.11.4 Low Power / Operating Modes

The DMADC1032 can be configured for lower MCU power consumption in different ways:

•

Disabled mode: After reset the ATD is disabled by default as the MDIS bit is set. Maximum power

saving is provided. Although disabled most of the registers remain accessible. For exceptions

please See 33.10.2.8 ATD Flag Register (ATDFLAG).

To execute conversions the ATD must first be enabled by clearing the MDIS bit.

•

Normal mode: To perform conversions, the ATD must be operating in Normal mode. To bring the

ATD into normal mode the MDIS bit must be cleared. This will enable the ATD clocks. Now all

registers are accessible and immediately a DMA-request for a command word is asserted. Also the

analog conversion circuit is powered up. But due to the recovery time tREC of the analog

conversion circuit, the result of conversions started before tREC has elapsed should be ignored as

the results will be unreliable.1

After the MDIS bit is set the ATD will return to Disabled mode. All clocks will be shut down and

the analog conversion circuit will power down. Therefore a running conversion will be terminated

and the command word in the ATDCW register will be discarded. The DMA request for a new

command word will be deasserted. A pending DMA request of a conversion result will remain

asserted until the ATD is enabled again and the result register is read.

•

Doze mode: The ATD will enter Doze mode when the ATDMODE.DOZE bit is set and the MCU

entered Doze mode. Otherwise the ATD will operate like in Normal mode. In Doze mode increased

power saving is provided as the clocks are disabled. Please refer to Chapter 3, “Low Power Modes”

for details on how to enter and exit low power modes.

Entering Doze mode will terminate any conversion currently running and will flush the command

queue. The DMA request for a new command word will be deasserted. A pending DMA request

of a conversion result will remain asserted until the ATD is enabled again and the result register is

read.

Although dozed most of the registers remain accessible. Please refer to Section 33.10, “Memory

Map and Register Definition” to identify which registers are not accessible.

To leave DOZE mode either the MCU has to leave Doze mode or the DOZE bit must be cleared.

1. Refer to Appendix A, “Electrical Characteristics” for recovery time tREC

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