MAC7200 datasheet(840/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

762

Freescale Semiconductor

33.11 Functional Description

33.11.1 General

The ATD performs analog to digital conversions using a redundant signed digit (RSD) architecture. The

ATD is divided into an analog and digital sub-blocks (see Figure 33-1):

The analog sub-block is responsible for multiplexing the various input voltage sources to a sample

capacitor. The voltage across this capacitor is compared with a reference voltage. This will deliver the raw

result to the digital block.

The digital block partly controls the analog part. E.g. it decides when to start conversions, how to

pre-discharge the sample capacitor, how long to sample etc. It also handles read/write accesses and

interrupts.

33.11.2 Analog Conversion Circuit

The analog conversion circuit contains all analog components required to perform a conversion according

to the RSD-algorithm. A separate power supply VDDA/VSSA allows noise isolation from other MCU

circuitry.

This block contains all sub-blocks mentioned in Section 33.11.2.1, “Analog Input Multiplexer” to

Section 33.11.2.4, “Conversion Circuit”.

NOTE

When the ATD is turned on for the first time, the analog conversion circuit

requires a recovery time tREC until reliable conversion results can be

determined1. Any conversion started/ended during that time should be

ignored.

33.11.2.1 Analog Input Multiplexer

The analog input multiplexer connects one of the 32 analog input channels to the sample capacitor.

33.11.2.2 Sample Capacitor

During the sampling phase the sample capacitor is connected to the analog input channel that is currently

converted.

33.11.2.3 Reference Voltage Generation

This block generates all reference voltages needed to determine the raw conversion result.

33.11.2.4 Conversion Circuit

The conversion circuit compares the sampled voltage with the reference voltages.

1. Refer to Appendix A, “Electrical Characteristics” for recovery time tREC

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