MAC7200 datasheet(839/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

761

NOTE

When converting any of the five ATD reference voltages the predischarge

feature must be enabled to reduce the influence of parasitic charges. The

predischarge time can be two ATD clock cycles or higher.

33.10.2.10 ATD Result Register (ATDRR)

This register contains the result for the last conversion that has been executed. As the result should never

be modified by anyone but the ATD conversion state machine, all bits of this register are read-only.

After a conversion, bits 31 to 16 of the finished command word will be copied to bits 31 to 16 of the result

conversion result. Each of the ATDRR[31:16] bits is prefixed with RR, rather than the CW prefix used in

the command word. For example, the RRCH bits have the same function as the CWCH bits. Refer to

Section 33.10.2.9, “ATD Command Word Register (ATDCW) for the function of each bit.

Bits 15 to 0 of the result register (RRCR) will contain the actual conversion result in the numeric format

specified by CWNF. For detailed information about the numeric formats see Figure 33-11 to Figure 33-14

and Table 33-17.

After a conversion, the ATD will assert a DMA request to store the result in memory. Once the result was

read by the MCU the DMA request will be deasserted.

If a result has not been read before a new conversion result arrives, a result loss will occur: The new

conversion result will overwrite the previous one and will set the CRL (conversion result loss) bit in the

flag register (ATDFLAG). Despite that, the ATD will continue executing conversions.

NOTE

If this register contains a conversion result any read access to this register

will mark the current result as read. If not all bytes of this register are read

before a new conversion result arrives no conversion result loss will be

flagged.

To avoid data corruption the software must read all relevant bytes of this

Address Base + 0x14

Access: User read

RRGI

RRCM

RRSL

RRNF

RRCH

Reset

000

876

321

RRRCR

Reset

000

Figure 33-15. ATD Result Register (ATDRR)

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