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MAC7200 Datasheet(PDF) 841 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 841 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
763
33.11.3 Digital Sub-blocks
This subsection describes the functions implemented in the digital part. See the register descriptions for
all details.
This block contains all sub-blocks mentioned in Section 33.11.3.1, “Mode / Timing Control” to
Section 33.11.3.8, “Conversion Control”.
33.11.3.1 Mode / Timing Control
The Timing Control is responsible for handling conversions by deciding which channel is to be converted,
when the conversion should start etc. It is responsible for the command/result transfer and the interrupt
generation.
33.11.3.2 Clock Prescaler
The frequency at which the analog conversion circuit can work is between 0.5 MHz and 12 MHz. A higher
system clock frequency must therefore be divided down to fit within this range. This division is provided
by the Clock Prescaler.
33.11.3.3 Bus Interface / Registers
The Bus interface handles read/write accesses from the MCU to the registers and DMA transfers of
conversion results or commands.
33.11.3.4 Command Word / Result / DMA
This block contains the command word queue which consists of ATDCW, ATDCC and ATDRR. It also
takes care of the DMA requests.
33.11.3.5 SYSTRIG0, SYSTRIG1 / External Trigger Input
Triggers can be used to initiate conversions that allow the synchronization of conversions to the external
environment, rather than relying on software to signal to the ATD module when conversions should take
place. The trigger source can be either from one of the analog inputs (from an external source) or from the
SYSTRIG0 / SYSTRIG1 inputs (trigger signals from counters). In this mode there is no access to the
registers.
The trigger is programmable to be edge or level sensitive with polarity control. In Section 33.10.2.2, “ATD
External Trigger Channel Register (ATDETRIGCH)” and Section 33.10.2.1, “ATD Trigger Control
Register (ATDTRIGCTL)” this is described in more details.
33.11.3.6 Flags
The flags reflect the current ATD status and can be used to generate interrupts.



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