MAC7200 datasheet(836/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

758

Freescale Semiconductor

ATD will not assert a DMA request for a new command. The DMA request for saving the

conversion result remains unaffected in both cases.

To start a new conversion, the MCU must write a new command word to the command register (see

Section 33.12.3.3, “Example 3: Interrupted Conversion Sequence”).

•

Convert then pause:

If a command word is currently being executed with CWCM = “convert then pause” the ATD will

stop converting after the conversion finished and will set the ATDFLAG.CP bit. No DMA request

for fetching a command word will be asserted. Only a DMA request for saving the result in the

memory will be asserted.

To start a new conversion the MCU must write a new command word (not “conversion reset”) to

the command register (Section 33.12.3.2, “Example 2: A Simple Conversion Sequence (Convert

then Pause)”).

•

Wait for trigger:

If a command word is currently being executed with CWCM = “wait for trigger”, the ATD will

start converting only after a valid trigger has been asserted. For setting the right trigger

source/behavior refer to Section 33.10.2.1, “ATD Trigger Control Register (ATDTRIGCTL) and

Section 33.10.2.2, “ATD External Trigger Channel Register (ATDETRIGCH).

See Section 33.12.3.4, “Example 4: Edge-triggered Conversion” and Section 33.12.3.5, “Example

5: Level-triggered Conversion” for examples about triggered conversions.

•

Convert continuously:

If a command word is currently being executed where CWCM = “convert continuously”, the ATD

will start a new conversion after the current conversion has finished and a new command word is

already available in ATDCW.

If there is no new command word available, the ATD will try to receive one by keeping a DMA

request asserted. After a new command word has been received from the DMA or the MCU, the

ATD will start a new conversion according to the new command word (see Section 33.12.3.6,

“Example 6: Queue Running Idle”).

The following figure shows how right-justified unsigned conversion will look in the RRCR. In the table,

‘Bit[x]’ reflect the bits determined by the successive approximation.

The following figure shows how an right-justified signed conversion will look in the RRCR. When using

“signed” arithmetic, the MSB of the conversion result must be copied to the bits that are not influenced by

RRCR

12 Bit

Bit11

MSB

Bit10

Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LSB

11 Bit

Bit11

MSB

Bit10

Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

10 Bit

Bit11

MSB

Bit10

Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

LSB

8 Bit

000

Bit11

MSB

Bit10

Bit9

Bit8

Bit7

Bit6

Bit5

Bit4

LSB

Figure 33-11. RRCR for Right Justified Unsigned

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