MAC7200 datasheet(916/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

838

Freescale Semiconductor

As an example, in Normal mode, with a 20Mhz bus clock (50ns period), tsetup = 200ns and thold = 200ns.

Figure 34-21 illustrates the timing parameters tsetup and thold. Six (6) bus clock cycles after the active edge

(assuming no filtered glitches), the PIFR bit will be set in the corresponding CONFIGxx register.

Figure 34-21. External Interrupt Timing Requirements

NOTE

The above illustration is for timing purposes only. Short (in duration)

changes during setup or hold will be filtered out by the glitch filter.

34.7.5

General Purpose Output mode

In General Purpose Output (GPO) mode, the pin is configured as an output, with full software control of

the pad.

34.7.5.1

Overview

GPO mode is set on a particular pin by clearing the MODE bit and setting the DDR bit in the pin’s

corresponding CONFIGxx register (See Section 34.8.2, “Using a Pin in GPIO Mode,” for an example).

In GPO mode, the following register bits are unused:

•

PIER (CONFIGxx[1])

•

PIFR (CONFIGxx[0])

NOTE

Even though the above bits are unused in this mode, they can still be written

to. The new values will take effect once the mode of the pin is switched to

GPI mode.

While in GPO mode, the data registers PORTDATA, PORTIR and PINDATAxx may be used as follows:

Table 34-52. Input Glitch Filter Requirements

System Mode

Minimum time negated before

active edge (tsetup)

Minimum time asserted after active

edge (thold)

Run (Normal)

4 x TBusClock

tsetup

thold

Rising Edge

Interrupt

Falling Edge

Interrupt

tsetup

thold

Active level

Passive level

Active level

Passive level

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