MAC7200 datasheet(914/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

836

Freescale Semiconductor

Figure 34-20 illustrates the anatomy of a single PIM pad cell in GPI mode.

Figure 34-20. Pad in GPI Mode (including pad PD2)

NOTE

The ODER bit and PORTDATA register are not available on Port E.

Table 34-50. PIM Register Behavior in GPI Mode

Write

Read

PORTDATA

Writing to the corresponding bit in the PORTDATA

set/clear the bit in the register. When the pin is

switched to General Purpose Output mode, the new

value will be driven onto the pin.

Reading from the PORTDATA register will return the

value driven on the pin, synchronized to the system

clock. This is identical to reading the corresponding

bit in the PORTIR register.

PORTIR

Writing to the PORTIR register will have no effect, as

it is a read-only register in all modes.

Reading from the PORTIR register will return the

value on the pin. Note that this value is internally

synchronized to the system clock, and that there is a

two clock cycle delay between the changing of the

value on the pin, and the update of the PORTIR

PINDATAxx

Writing to the PINDATAxx register is identical to

writing the corresponding bit in the PORTDATA

Reading from the PINDATAxx register is identical to

reading the corresponding bit from the PORTDATA

PINDATAxx/

PORTIR[x]

ODER

SYNC

PORTDATA[x]

Analog Input Data to Peripheral

Digital Input Data to Peripheral

Control signals from the PIM

Data registers in the PIM

PULL[1:0]

(Tied low)

Glitch

Filter

PIER

PIFR

Interrupt

PAD

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