MAC7200 datasheet(954/976 Pages) FREESCALE

954 / 976 page

External Interrupt Inputs (IRQ/XIRQ)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

876

Freescale Semiconductor

Figure A-4. Nexus Output Timing Specifications

A.12

External Interrupt Inputs (IRQ/XIRQ)

Note that both the IRQ and XIRQ inputs are synchronized internally, so no setup or hold timings are

required. Consequently, the input signal must be held long enough to be synchronized.

A.13

JTAG Port Timing

Table A-24 lists JTAG Port timings, which are shown in Figure A-5.

NOTE

All JTAG input and output timings are synchronous; that is, input setup/hold

and output delay with respect to the rising edge of a reference clock. The

reference clock is the TCK input.

All other timing relationships can be derived from these values.

Table A-22. Nexus Output Timing Specifications

Num

Rating1

1. Timing specifications have been indicated taking into account the full slew rate for the pads and 30 pF output load.

Symbol

Min

Typ

Max

Unit

D MCKO

tCYC

—

Data Outputs

D MCKO low to Nexus Output valid

tCLPOV

——

3.5

D MCKO low to Nexus Output invalid

tCLPOI

–5.5

—

Table A-23. External Interrupt Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

D Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ

4—

—

tSYS

1. tSYS = 1/fSYS. See parameter C7.

Table A-24. JTAG Port Timing

Num

Rating1

Symbol

Min

Typ

Max

Unit

D TCK Frequency of Operation

fJCYC

—

fSYS / 8

MHz2

D TCK Cycle Period

tJCYC

8—

—

tSYS

MCKO

Outputs

2.5V

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