MAC7200 datasheet(956/976 Pages) FREESCALE

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DSPI Timing

MAC7200 Microcontroller Family Reference Manual, Rev. 2

878

Freescale Semiconductor

Figure A-6. SPI Master Timing (CPHA = 0)

D Enable Lead Time

tLEAD

0.5

—

tSCK

D Enable Lag Time

tLAG

0.5

—

tSCK

D Clock (SCK) Duty Cycle

tDUTY

—

D Data Setup Time (Inputs)

tsu

—

D Data Hold Time (Inputs)

thi

-6

—

D Data Valid (after Enable Edge)

——

D Data Valid (after ChipSelect Edge)

——

D Data Hold Time (Outputs)

tho

-3

—

1. Refer to Chapter 30, “Deserial Serial Peripheral Interface (DSPI)” for all available baud rates.

2. See parameter S1b.

Table A-25. SPI Master Mode Timing Characteristics (Continued)

Conditions are shown in Table A-5 unless otherwise noted, CLOAD = 30 pF on all outputs

MSB Out(2)

MSB In(2)

PCSx

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

Bit 6

… 1

SIN

(INPUT)

SOUT

(OUTPUT)

LSB Out

LSB In

Bit 6

… 1

S1b

1 If configured as output.

2 LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1,

… bit 6, MSB.

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