MAC7200 datasheet(957/976 Pages) FREESCALE

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DSPI Timing

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

879

Figure A-7. SPI Master Timing (CPHA = 1)

A.14.2

Slave Mode

Slave mode timing values are shown in Table A-26 and illustrated in Figure A-8 and Figure A-9.

Table A-26. SPI Slave Mode Timing Characteristics

Conditions are shown in Table A-5 unless otherwise noted, CLOAD = 30 pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

T1a

D Operating Frequency

fOP

see S1a

T1b

D SCK Period (tSCK = 1 / fOP)tSCK

see S1b

D Enable Lead Time

tlead

1—

—

tSYS

D Enable Lag Time

tlag

1—

—

tSYS

D Clock (SCK) Duty Cycle

tDUTY

—

T5a

D Data Setup Time (Inputs) (CPHA=0)

tsu

—

T5b

D Data Setup Time (Inputs) (CPHA=1)

tsu

—

T6a

D Data Hold Time (Inputs) (CPHA=0)2

thi

—

T6b

D Data Hold Time (Inputs) (CPHA=1)

thi

-6

—

D Slave Access Time

——

tSYS

D Slave SIN Disable Time

tdis

——

tSYS

T9a

D Data Valid (after SCK Edge) (CPHA=0)

—

T9b

D Data Valid (after SCK Edge) (CPHA=1)

—

PCSx

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

Bit 6

… 1

SIN

(INPUT)

SOUT

(OUTPUT)

LSB In

Bit 6

… 1

Port Data

Master LSB Out

S1b

MSB Out(2)

MSB In(2)

1 If configured as output.

2 LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1,

… bit 6, MSB.

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