MAC7200 datasheet(955/976 Pages) FREESCALE

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DSPI Timing

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

877

Figure A-5. JTAG Port Timing Specifications

A.14

DSPI Timing

A.14.1

Master Mode

Master mode timing values are shown in Table A-25 and illustrated in Figure A-6 and Figure A-7.

D TCK Clock Pulse Width

tJCW

2—

—

tSYS

D TMS, TDI Input Data Setup Time to TCK Rise

tTAPBST

1—

—

tSYS

D TMS, TDI Input Data Hold Time after TCK Rise

tTAPBHT

1—

—

tSYS

D TCK Fall to TDO Data Valid

tTDODV

——

tSYS

D TCK Fall to TDO Data Invalid

tTDODI

1—

—

tSYS

1. Timing specifications have been indicated taking into account the full slew rate for the pads.

2. See parameter C7.

3. tSYS = 1/fSYS. See parameter C7.

Table A-25. SPI Master Mode Timing Characteristics

Conditions are shown in Table A-5 unless otherwise noted, CLOAD = 30 pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

S1a

D Operating Frequency (baud rate)

fOP

——

MHz

S1b

D SCK Period

tSCK

tSCK = 1 / fOP

Table A-24. JTAG Port Timing (Continued)

Num

Rating1

Symbol

Min

Typ

Max

Unit

TCK

TMS,TDI

TCK

TDO

Output Data Valid

TDO

Output Data Invalid

2.5V

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