LPC1850 datasheet(23/84 Pages) NXP

23 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

23 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

PD_14[2]

R13

<tbd>

n.c.

-n.c.

EXTBUS_DYCS2 — SDRAM chip select 2.

-n.c.

PD_15[2]

T15

<tbd>

n.c.

-n.c.

I/O

EXTBUS_A17 — External memory address line 17.

-n.c.

PD_16[2]

R14

<tbd>

n.c.

-n.c.

I/O

EXTBUS_A16 — External memory address line 16.

-n.c.

PE_0[2]

P14

<tbd>

n.c.

-n.c.

I/O

EXTBUS_A18 — External memory address line 18.

PE_1[2]

N14

<tbd>

n.c.

-n.c.

I/O

EXTBUS_A19 — External memory address line 19.

PE_2[2]

M14

<tbd>

ADCTRIG0 — ADC trigger input 0.

CAN1_RD — CAN1 receiver input.

I/O

SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.

I/O

EXTBUS_A20 — External memory address line 20.

PE_3[2]

K12

<tbd>

n.c.

CAN1_TD — CAN1 transmitter output.

ADCTRIG1 — ADC trigger input 1.

I/O

EXTBUS_A21 — External memory address line 21.

PE_4[2]

K13

<tbd>

n.c.

NMI — External interrupt input to NMI.

-n.c.

I/O

EXTBUS_A22 — External memory address line 22.

PE_5[2]

N16

<tbd>

n.c.

CTOUT_3 — SCT output 3. Match output 3 of timer 0.

U1_RTS — Request to Send output for UART 1. Can also be configured to be

an RS-485/EIA-485 output enable signal for UART 1.

I/O

EXTBUS_D24 — External memory data line 24.

Table 3.

Pin description …continued

Symbol

Reset

state

[1]

Type Description

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