LPC1850 datasheet(37/84 Pages) NXP

37 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

37 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.12 AHB peripherals

7.12.1 State Configurable Timer (SCT) subsystem

The SCT allows a wide variety of timing, counting, output modulation, and input capture

operations. The inputs and outputs of the SCT are shared with the capture and match

inputs/outputs of the 32-bit general purpose counter/timers.

The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the

two-counter case, in addition to the counter value the following operational elements are

independent for each half:

• State variable

• Limit, halt, stop, and start conditions

• Values of Match/Capture registers, plus reload or capture control values

In the two-counter case, the following operational elements are global to the SCT, but the

last three can use match conditions from either counter:

• Clock selection

• Inputs

• Events

• Outputs

• Interrupts

7.12.1.1

Features

• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.

• Up counter(s) or up-down counter(s).

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs and interrupts.

• Selected event(s) can limit, halt, start, or stop a counter.

• Supports:

– up to 8 inputs (one input connected internally)

– up to 16 outputs

– 16 match/capture registers

– 16 events

– 32 states

7.12.2 General Purpose DMA (GPDMA)

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

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