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LPC1850 Datasheet(PDF) 53 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 84 page ![]() LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 — 3 January 2011 53 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 8. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(IO) I/O supply voltage 2.2 - 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.2 - 3.6 V VDDA(3V3) analog supply voltage (3.3 V) 2.0 - 3.6 V VBAT battery supply voltage [2] 2.2 - 3.6 V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from <tbd>; all peripherals disabled CCLK = 12 MHz; PLL disabled [3] -<tbd> -mA CCLK = 100 MHz; PLL enabled [3] -<tbd> -mA CCLK = 150 MHz; PLL enabled [3] -<tbd> -mA sleep mode [3] -<tbd> -mA deep sleep mode [3][4] -<tbd> - μA power-down mode [3][4] -<tbd> - μA deep power-down mode; RTC not running [3] -<tbd> -nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [5] -<tbd> -nA VDD(REG)(3V3) not present [6] - <tbd> - nA IDD(IO) I/O supply current deep sleep mode [7] -<tbd> -nA power-down mode [7] -<tbd> -nA deep power-down mode [7] -<tbd> -nA IDD(ADC) ADC supply current deep sleep mode [8] -<tbd> -nA power-down mode [8] -<tbd> -nA deep power-down mode [8] -<tbd> -nA |
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