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LPC1850 Datasheet(PDF) 29 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 84 page  LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 — 3 January 2011 29 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller [1] I = input, O = output, IA = inactive; PU = pull-up enabled; F = floating [2] Digital I/O pin. Not 5 V tolerant. [3] Digital I/O pin. 5 V tolerant. [4] Digital high-speed I/O pin. [5] 5 V tolerant analog I/O pin. [6] 3.3 V tolerant analog I/O pin. [7] 5 V tolerant USB I/O pin. [8] I2C-bus 5 V tolerant open-drain pin. [9] Reset input pin; <tbd>. [10] Alarm output pin; <tbd>. VSSIO G6; J8; J9; K9; K10; P7; M13; P13; D13; G8; H8; G7; C4; H9 Ground Pins not connected - B9 - n.c. Table 3. Pin description …continued Symbol Reset state [1] Type Description |
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