LPC1850 datasheet(6/84 Pages) NXP

6 / 84 page

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 3 January 2011

6 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

Pinning information

6.1 Pinning

6.2 Pin description

On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA

to PF, with up to 20 pins used per port. Each digital pin may support up to four different

digital functions, including General Purpose I/O (GPIO), selectable through the SYSCON

registers. Note that the pin name is not indicative of the GPIO port assigned to it.

Analog functions and power pins are pinned out separately and do not share pins with

digital functions.

Fig 2.

Pin configuration LBGA256 package

002aaf230

LPC1850/30FET256

Transparent top view

2468

13579

ball A1

index area

Table 3.

Pin description

Symbol

Reset

state

[1]

Type Description

Multiplexed digital pins

P0_0[2]

I; PU

I/O

GPIO0[0] — General purpose digital input/output pin.

I/O

SSP1_MISO — Master In Slave Out for SSP1.

ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

-n.c.

P0_1[2]

I; PU

I/O

GPIO0[1] — General purpose digital input/output pin.

I/O

SSP1_MOSI — Master Out Slave in for SSP1.

ENET_COL — Ethernet Collision detect (MII interface).

-n.c.

LPC1850 Datasheet(PDF) 6 Page - NXP Semiconductors

LPC1850 Datasheet(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL