LPC1850 datasheet(32/84 Pages) NXP

32 / 84 page

LPC1850_30_20_10

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Objective data sheet

Rev. 1 — 3 January 2011

32 of 84

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.4.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.5 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up

signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,

and Deep power-down modes. Individual events can be configured as edge or level

sensitive and can be enabled or disabled in the event router. The event router can be

battery powered.

The following events if enabled in the event router can create a wake-up signal and/or an

interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC, WWDT, BOD interrupts

• C_CAN and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCT and timer0/1/3)

7.6 System Tick timer (SysTick)

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.7 On-chip static RAM

The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for

higher throughput and individual power control for low power operation.

7.8 Boot ROM

The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After

a reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• ROM memory size is 32 kB.

• Supports booting from UART interfaces and external static memory such as NOR

flash, SPI flash, quad SPI flash.

• Includes APIs for power control and OTP programming.

• Includes SPIFI and USB drivers.

AES capable parts also support:

• CMAC authentication on the boot image.

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