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LPC1850 Datasheet(PDF) 69 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 84 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11.7 Static external memory interface Table 16. Dynamic characteristics: Static external memory interface CL =30 pF; Tamb = −40 °C to 85 °C; VDD(REG)(3V3) and VDD(IO) over specified ranges <tbd>; AHB clock = 1 MHz Symbol Parameter Conditions Min Typ Max Unit Common to read and write cycles[1] tCSLAV CS LOW to address valid time <tbd> <tbd> <tbd> ns Read cycle parameters[1][2] tOELAV OE LOW to address valid time <tbd> <tbd> <tbd> ns tCSLOEL CS LOW to OE LOW time <tbd> + Tcy(CCLK) × WAITOEN 0 + Tcy(CCLK) × WAITOEN <tbd> + Tcy(CCLK) × WAITOEN ns tam memory access time [3][4] (WAITRD − WAITOEN + 1) × Tcy(CCLK) − <tbd> (WAITRD − WAITOEN + 1) × Tcy(CCLK) − <tbd> (WAITRD − WAITOEN + 1) × Tcy(CCLK) − <tbd> ns th(D) data input hold time [5] <tbd> <tbd> <tbd> ns tCSHOEH CS HIGH to OE HIGH time <tbd> <tbd> <tbd> ns tOEHANV OE HIGH to address invalid time <tbd> <tbd> <tbd> ns tOELOEH OE LOW to OE HIGH time <tbd> + (WAITRD − WAITOEN + 1) × T cy(CCLK) 0 + (WAITRD − WAITOEN + 1) × T cy(CCLK) <tbd> + (WAITRD − WAITOEN + 1) × T cy(CCLK) tBLSLAV BLS LOW to address valid time <tbd> <tbd> <tbd> ns tCSHBLSH CS HIGH to BLS HIGH time <tbd> <tbd> <tbd> ns Write cycle parameters[1][6] tCSLWEL CS LOW to WE LOW time <tbd> + Tcy(CCLK) × (1 + WAITWEN) <tbd> + Tcy(CCLK) × (1 + WAITWEN) <tbd> + Tcy(CCLK) × (1 + WAITWEN) ns tCSLBLSL CS LOW to BLS LOW time −0.88 0.49 0.98 ns tWELDV WE LOW to data valid time 0.68 2.54 5.86 ns tCSLDV CS LOW to data valid time 0 2.64 4.79 ns tWELWEH WE LOW to WE HIGH time [3] <tbd> + Tcy(CCLK) × (WAITWR − WAITWEN + 1) 0 + Tcy(CCLK) × (WAITWR − WAITWEN + 1) <tbd> + Tcy(CCLK) × (WAITWR − WAITWEN + 1) ns tBLSLBLSH BLS LOW to BLS HIGH time [3] <tbd> + Tcy(CCLK) × (WAITWR − WAITWEN + 3) 0 + Tcy(CCLK) × (WAITWR − WAITWEN + 3) <tbd> + Tcy(CCLK) × (WAITWR − WAITWEN + 3) ns tWEHANV WE HIGH to address invalid time [3] <tbd> + Tcy(CCLK) <tbd> + Tcy(CCLK) <tbd> + Tcy(CCLK) ns |
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