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PCF8537 Datasheet(PDF) 17 Page - NXP Semiconductors |
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PCF8537 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 82 page ![]() PCF8537 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 31 May 2012 17 of 82 NXP Semiconductors PCF8537 Industrial LCD driver for multiplex rates up to 1:8 8.2 Start-up and shut-down 8.2.1 Power-On Reset (POR) At power-on, the PCF8537 resets to starting conditions as follows: 1. All backplane and segment outputs are set to VSS. 2. Selected drive mode is: 1:8 with 1⁄4 bias. 3. Input and output bank selectors are reset. 4. The I2C-bus and SPI-bus interface are initialized. 5. The data pointer is cleared (set logic 0). 6. The internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in 3-state. 7. Temperature measurement is enabled. 8. Temperature filter is disabled. 9. The internal VLCD voltage generation is disabled. The charge pump is switched off. 10. The VLCD temperature compensation is enabled. 11. The display is disabled. The reset state is as shown in Table 23. Remark: Do not transfer data on the I2C-bus or SPI-bus for at least 1 ms after a power-on reset to allow the reset action to complete. Table 23. Reset state Reset state of configuration bits shown in the command table format for clarity. The bit labeled with - has an undefined reset state. Command name Bits 7 6 5 4 3 2 1 0 Oscillator-ctrl 110 011 COE = 0 OSC = 0 Charge-pump-ctrl 1 1 0 0 0 0 CPE = 0 CPC = 0 Temp-msr-ctrl 110 010 TCE = 1 TME = 1 Temp-comp 000 11SLA[2:0] = 000 001 00SLB[2:0] = 000 001 01SLC[2:0] = 000 001 10SLD[2:0] = 000 Set-VPR 0 1 0 0 VPR[7:4] = 0000 0 1 0 1 VPR[3:0] = 0000 Display-enable 001 110 0E = 0 Set-MUX-mode 000 00M[2:0] = 000 Set-bias-mode 1 1 0 0 0 1 B[1:0] = 00 Load-data-pointer 1 0 P[5:0] is undefined Frame-frequency 0 1 1 F[4:0] = 01110 Bank-select 0 0 0 0 1 0 IBS = 0 OBS = 0 Invmode_ctrl 1 1 0 1 0 1 LF = 0 - Temp-filter 110 100 1TFE = 0 |
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