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AM79C976 Datasheet(PDF) 239 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 239 Page - Advanced Micro Devices |
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239 / 309 page  8/01/00 Am79C976 239 P R E L I M INARY The following tables describe the transmit descriptor bits in more detail. 7DEOH 7UDQVPLW'HVFULSWRU 6:67</( 7DEOH7UDQVPLW'HVFULSWRU 6:67</( Offset 31 30 29 28 27-26 25 24 23 22 21-18 17-16 15-0 00h OWN ADD_ FCS LTINT STP ENP KILL BCNT 04h TCC[1:0] TCI[15:0] 08h TBADR[31:0] 0Ch TBADR[63:32] 10h Reserved 14h USER SPACE 18h USER SPACE 1Ch USER SPACE Offset Bit Name Description 0 15-0 TBADR[15:0] Transmit Buffer Address. This field contains the high order bits of the address of the Transmit buffer that is associated with this descriptor. 215 OWN This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by the Am79C976 controller (OWN = 1). The host sets the OWN bit after filling the buffer pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after transmitting the contents of the buffer. Both the Am79C976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 2 14 Reserved location . 2 13 ADD_FCS ADD_FCS dynamically controls the generation of FCS on a frame by frame basis. This bit should be set with the ENP bit. However, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. When ADD_FCS is set, the state of DXMTFCS is ignored and transmitter FCS generation is activated. When ADD_FCS is cleared to 0, FCS generation is controlled by DXMTFCS. When APAD_XMT (CSR4, bit 11) is set to 1, the setting of ADD_FCS has no effect. ADD_FCS is set by the host, and is not changed by the Am79C976 controller. This is a reserved bit in the C-LANCE (Am79C90) controller. 212 LTINT Last Transmit Interrupt. When enabled by the LTINTEN bit (CSR5, bit 14), LTINT is used to suppress interrupts after selected frames have been copied to the transmit FIFO. When LTINT is cleared to 0 and ENP is set to 1, the Am79C976 controller will not set TINT (CSR0, bit 9) after the corresponding frame has been copied to the transmit FIFO. TINT will only be set when the last descriptor of a frame has both LTINT and ENP set to 1. When LTINTEN is cleared to 0, the LTINT bit is ignored. 2 11-10 Reserved. 29 STP Start of Packet indicates that this is the first buffer to be used by the Am79C976 controller for this frame. It is used for data chaining buffers. The STP bit must be set in the first buffer of the frame, or the Am79C976 controller will skip over the descriptor and poll the next descriptor(s) until the OWN and STP bits are set. STP is set by the host and is not changed by the Am79C976 controller. 28 ENP End of Packet indicates that this is the last buffer to be used by the Am79C976 controller for this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame fits into one buffer and there is no data chaining. ENP is set by the host and is not changed by the Am79C976 controller. |
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