AM8530 datasheet(23/194 Pages) AMD

23 / 194 page

System Interface

AMD

2–5

2.3

SYSTEM TIMINGS

Two control signals,

RD and WR, are used by the SCC to time bus transactions. In addi-

tion, four other control signals,

CE, D/C, A/B and INTACK are used to control the type of

bus transaction that will occur.

A bus transaction starts when the D/

C and A/B pins are asserted prior to the negative

edge of the

RD or WR signal. The coincidence of CE and RD or CE and WR latches the

state of D/

C and A/B and starts the internal operation. The INTACK signal must have

been previously sampled High by a rising edge of PCLK for a read or write cycle to occur.

In addition to sampling

INTACK, PCLK is used by the interrupt section to set the Interrupt

Pending (IP) bits.

The SCC generates internal control signals in response to a register access. Since

and

WR have no phase relationship with PCLK, the circuitry generating these internal

control signals provide time for metastable conditions to disappear. This results in a re-

covery time related to PCLK. This recovery time applies only between transactions involv-

ing the Am8530H/Am85C30, and any intervening transactions are ignored. This recovery

time is four PCLK cycles, measured from the falling edge of

RD or WR for a read or write

cycle of any SCC register on the Am8530H-step and 3 or 3.5 PCLK cycles for the

Am85C30.

Note that

RD and the WR inputs are ignored until CE is activated. The falling edge of RD

and

WR can be substituted for the falling edge of CE or vice versa for calculating proper

pulse width for

RD or WR low. In other words, if CE goes active after RD or WR have

gone active for a read or a write cycle, respectively,

CE must stay active as long as the

minimum pulse width for

RD and WR.

2.3.1

Read Cycle

The Read cycle timing for the SCC is shown in Figure 2–1. The A/

B and D/C pins are

latched by the coincidence of

RD and CE active. CE must remain Low and INTACK must

remain High throughout the cycle. The SCC bus drivers are enabled while

CE and RD are

both Low. A read with D/

C High does not disturb the state of the pointers and a read cycle

with D/

C Low resets the pointers to zero after the internal operation is complete.

2.3.2

Write Cycle

The Write cycle timing for the SCC is shown in Figure 2–2. The A/

B and D/C pins are

latched by the coincidence of

WR and CE active. CE must remain Low and INTACK must

remain High throughout the cycle. A write cycle with D/

C High does not disturb the state

of the pointers and a write cycle with D/

C Low resets the pointers to zero after the internal

operation is complete.

2.3.3

Interrupt Acknowledge Cycle

The Interrupt Acknowledge cycle timing for the SCC is shown in Figure 2–3. The state of

INTACK is latched by the rising edge of PCLK. While INTACK is Low, the state of the

B, D/C, and WR pins is ignored by the SCC. Between the time INTACK is first sampled

Low and the time

RD falls, the internal and external IEI/IEO daisy chains settle; this is

A.C. parameter #38 TdlAi (RD).

If there is an interrupt pending in the SCC, and IEI is High when

RD falls, the Interrupt

Acknowledge cycle is intended for the SCC. This being the case, the SCC sets the appro-

priate Interrupt Under Service (IUS) latch, and places an interrupt vector on D0–D7. If the

falling edge of

RD sets an IUS bit in the SCC, the INT pin goes inactive in response to the

falling edge. Note that there should be only one

RD per Acknowledge cycle.

Another important fact is that the IP bits in the SCC are updated by a clock half the fre-

quency of PCLK, and this clock is stopped while the pointers point to RR2 and RR3; thus

the interrupt requests will be delayed if the pointers are left pointing at these registers.

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