AM8530 datasheet(72/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–20

The address comparison will be across all eight bits of WR6 when the Sync Character

Load Inhibit bit (D1 in WR3) is set to ‘0’. This comparison may be modified so that only

the four most significant bits of WR6 must match the received address. This mode is se-

lected by programming WR3 as shown below.

D6 D5

D4 D3

D2 D1

WR3—Register Layout

In this mode, however, the address field is still eight bits wide. Regardless of the mode

enabled, the address field is not treated differently than data and is always transferred to

the Receive Data FIFO in the same manner as data. Note that Address Search mode is

available only in SDLC mode.

SDLC address search mode (bit D2 in Write Register 3 is set) and Receive Full CRC

mode (bit D5 of Write Register 7

′) should not be used in conjunction with each other. If

these modes are used together, the Am85C30 will accept all packets with addresses that

match the address programmed into Register 6 and will accept only the address byte of

the packet with addresses that do not match the Register 6 address. Proper operation of

address search mode calls for the complete rejection of packets with addresses that do

not match the Register 6 address.

4.7.1.5

Abort Detection

In addition to monitoring the data stream for flags, the receiver also monitors the line for

an abort pattern. An abort is detected when seven consecutive ‘1’s are found in the data

stream. This is usually an indication sent by the transmitter alerting the receiver that the

frame currently being received has been aborted and should be discarded.

The detection of an abort is reported in the BREAK/ABORT status bit in RR0 (D7). This

status bit is one source of External/Status interrupts, so transitions of this status bit may

be programmed to cause interrupts.

An abort automatically forces the receiver into Hunt mode and sets the SYNC/HUNT

status bit in RR0 (D4) to ‘1’. Because this status bit is also a possible External/Status con-

dition, its transition may also be programmed to cause an interrupt. Thus transitions on

both the BREAK/ABORT and SYNC/HUNT status bits may occur very close together, and

either one or two External/Status interrupts may result.

The BREAK/ABORT status bit will be reset when a ‘0’ is received, either by the abort it-

self going away or as the leading ‘0’ of a flag. In either case, the SYNC/HUNT status bit

will remain set until the receiver leaves Hunt mode. Because both transitions on the

BREAK/ABORT status bit are guaranteed to cause an interrupt, two discrete External/

Status Interrupts will occur; one when the abort is detected and one when the abort goes

away.

Note that the SCC does not discriminate between an in-frame (between opening and

closing flags) and an out-of-frame (after EOF) abort. An abort detected while the receiver

is In-Frame terminates frame reception, but not in an orderly manner, because the char-

acter being assembled is lost and the Receive Data FIFO is not flushed. An out-of-frame

abort interrupt will be generated approximately seven bit times after EOF has been de-

tected if the transmitter mark idles. If an ABORT is detected by the receiver after the clos-

ing flag and eight 1s have been received, the ABORT will persist until another flag is de-

tected at which time the receiver exits from Hunt Mode. If an out-of-frame interrupt is to

be avoided it should be disabled early in the EOF interrupt routine. Because the BREAK/

ABORT status bit is not latched in RR0, it may happen that this status bit will be reset by

the time the software responds to the interrupt, causing yet another interrupt. In this case,

unless the DCD pin has been programmed as the receiver Auto Enable, the SYNC/HUNT

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