AM8530 datasheet(74/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–22

Because the bit pattern used by the receiver for CRC error checking is based on an in-

dustry standard polynomial, only the CRC-CCITT polynomial (X16+X12+X5+1) can be

used in SDLC mode.

The CRC transmission and CRC-CCITT polynomial are enabled by programming WR5 as

shown below.

D6 D5

D4 D3

D2 D1

WR3—Register Layout

4.7.2.1

Rx CRC Initialization

Bit D7 of WR10 controls the initial state of both the transmit and receive CRC generators.

Although the transmit and receive generators may be preset to either all ‘0’s or all ‘1’s,

SDLC operation requires that this bit be set to ‘1’ for proper error detection.

The receive CRC generator will be automatically preset whenever the receiver is in Hunt

mode, or a flag is detected so a Reset CRC Checker command should not be necessary.

It may, however, be preset whenever necessary by issuing this command in WR0.

4.7.2.2

Rx CRC Enabling

In SDLC Mode, the SCC always calculates CRC on all bits, except inserted zeros, be-

tween the opening and closing flags of a frame, so the Rx CRC Enable bit in WR3 (D3) is

ignored.

4.7.2.3

CRC Error

When the end of frame flag is detected, the CRC Error bit is loaded into the Receive Error

FIFO at the same time the character in the Receive Shift Register is transferred to the

Receive Data FIFO. Since this CRC Error status bit is not latched internally, it will usually

always be set to ‘1’ in RR1, since most bit combinations, except for a correctly completed

frame, result in a non-zero CRC. Hence, the CRC Error bit should not be considered valid

until the EOF status bit is set to ‘1’ in RR1, and should be ignored at all other times.

4.7.2.4

CRC Character Reception

On the NMOS SCC, when the end of frame flag is detected the contents of the Receive

Shift Register are transferred to the Receive Data FIFO regardless of the number of bits

accumulated. Because of the 3-bit delay between the Receive SYNC Register and Re-

ceive Shift Register, the last two bits of the CRC check character received are never

transferred to the Receive Data FIFO. Thus, the received CRC characters are unavailable

for use.

On the CMOS SCC, the option of being able to receive the complete CRC characters

generated by the transmitter is provided when both bits D0 of WR15 and bit D5 of WR7’

are set to ‘1’. When these two bits are set and an end of frame flag is detected, the last

two bits of the CRC will be clocked into the Receive Shift Register before its contents are

transferred to the Receive Data FIFO. The data-CRC boundary and CRC character bit

formats for each Residue Code provided are shown in Figures 4–15 through 4–18 for

each character length selected.

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