AM8530 datasheet(58/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–6

SDLC Mode

MONOSYNC Mode

BISYNC Mode

ASYNC Mode

— 1 Stop Bit

— 1 1/2 Stop Bits

— 2 Stop Bits

WR4

WR4—Mode Settings

4.4

RECEIVER OVERVIEW

The receiver performs all the functions necessary to convert serial data back to parallel

for the processor. The receiver block diagram is shown in Figure 4–5.

Serial data on the RxD pin is sampled on the rising edge of RTxC and passes through a

one bit delay before either passing to the NRZI decode logic, or, depending on the mode,

the Receive SYNC Register, 3-bit delay, or Receive Shift Register. Once a character has

been assembled in the Receive Shift Register it is transferred to the 3 x 8-bit Receive

Data FIFO, and the Receive Character Available status bit in RR0 (D0) is set to alert the

processor that a character is available. This arrangement creates a 3-byte delay time

which allows the CPU time to service an interrupt at the beginning of a block of high-

speed data.

Every character transferred to the Receive Data FIFO is checked for errors, or Special

Conditions, by the Receive Error Logic. This status is loaded into the Receive Error FIFO

so that the status associated with each character can be read with that character through

RR1. If receive interrupts are disabled then reading a character from the Receive Data

FIFO moves the next character and its status to the top of the FIFO; so if status is needed

for a character received, RR1 must be read prior to reading RR8 (Receive Buffer). If

status is read after the data is read, the error data, if any, for the next character in the Er-

ror FIFO will be included also. If, however, operations are being performed rapidly

enough before the next character is received, then the status will be valid. However, if

certain receive interrupts are enabled, the interrupt will not be generated until the charac-

AM8530 Datasheet(PDF) 58 Page - Advanced Micro Devices