AM8530 datasheet(81/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–29

The Tx Underrun/EOM status bit in RR0 will be set to ‘1’ by the SCC to indicate that an

underrun has occurred, and that either the CRC, or abort character, has been loaded into

the Transmit Shift Register for transmission. The Low-to-High transition of this bit may be

programmed to generate an External/Status interrupt or, if interrupts are disabled, may be

polled in RR0.

Hence, if the CRC check characters are to be properly appended to a frame, the Abort/

Flag on Underrun bit must be set to ‘0’, and the Reset Tx Underrun/EOM Command must

be issued after the first but before the last character is written to the Transmit Buffer. This

will ensure that either an abort or the CRC will be transmitted if an underrun occurs. Nor-

mally, the Abort/Flag on Underrun bit in WR10 should be set to ‘1’ around the same time

that the Tx Underrun/EOM bit is reset so that an abort will be sent if the transmitter acci-

dentally underruns, and then set to ‘0’ near the end of the frame to allow the correct trans-

mission of CRC.

Note that the Reset Tx Underrun/EOM command will not reset the status bit latch if the

transmitter is disabled. However, if no External/Status interrupts are pending, or if a Reset

External/Status Interrupt command accompanies this command while the transmitter is

disabled, an External/Status interrupt will be generated with the Tx Underrun/EOM bit

reset in RR0.

4.8.7

Auto Tx Underrun/EOM Latch Reset

On the CMOS SCC, if bit D0 of WR15 is set to ‘1’, the option of having the Tx Underrun/

EOM bit be reset automatically at the start of every frame is provided via bit D1 of WR7’.

This helps alleviate the software burden of having to respond within one character time

when high speed data are being sent.

4.8.8

Transmitter Disabling

The transmitter is enabled/disabled via bit D3 of WR5. Data transmission from the SCC

does not begin until this bit is set to ‘1’. Disabling the transmitter can be done at any time,

but if disabled during transmission of a character, that character will be “completely sent.”

This applies to both data and flags. However, if the transmitter is disabled during the

transmission of CRC, the 16-bit transmission will not be completed and the remaining bits

will be from WR7 (flag character).

In the paragraph above, the term “completely sent” means shifted out the Transmit Shift

On the NMOS SCC, if NRZI encoding is being used and the Transmitter is disabled the

state of the TxD pin will depend on the last bit sent. That is, the TxD pin may either idle in

a Low or High state as shown below in Figure 4–19. Although, in full-duplex applications

this may not be a problem, in half-duplex applications the TxD pin must be pulled high in

order to allow proper reception of data.

4.8.9

NRZI Mode Transmitter Disabling

On the CMOS SCC, an option is provided that allows setting the TxD pin High when oper-

ating in SDLC Mode with NRZI encoding enabled. If bit D0 of WR15 is set to ‘1’, then bit

D3 of WR7’ can be used to set the TxD pin High. Note that the operation of this bit is in-

dependent of the Tx Enable bit in WR5. The Tx Enable bit in WR5 is used to disable and

enable the transmitter, whereas bit D3 of WR7’ acts as a pseudo transmitter disable and

enable by just forcing the TxD pin High when set even though the transmitter may actu-

ally be mark or flag idling. Care must be used when setting this bit because any character

being transmitted at the time this bit is set will be “chopped off,” and data written to the

transmit buffer while this bit is set will be lost.

When the transmit underrun occurs and the CRC and closing flag have been sent, bit D3

can be set to pull TxD High. When ready to start sending data again this bit must be reset

to ‘0’ before the first character is written to the transmit buffer. Note that resetting this bit

causes the TxD pin to take whatever state the NRZI encoder is in at the time so synchro-

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