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AM8530 Datasheet(PDF) 30 Page - Advanced Micro Devices

Part # AM8530
Description  Serial Communications Controller
PDF  194 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM8530 Datasheet(HTML) 30 Page - Advanced Micro Devices

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System Interface
AMD
2–12
If both bits D0 and D2 of WR15 are set to ‘1’ then the Am85C30 register map is as shown
in Table 2–6.
Table 2–6. Register Set—All Enhancements Enabled
A/B
PNT2
PNT1
PNT0
WRITE
READ
0
0
0
0
WR0B
RR0B
0
0
0
1
WR1B
RR1B
0
0
1
0
WR2
RR2B
0
0
1
1
WR3B
RR3B
0
1
0
0
WR4B
RR4B(WR4B)
0
1
0
1
WR5B
RR5B(WR5B)
0
1
1
0
WR6B
RR6B
0
1
1
1
WR7B
RR7B
1
0
0
0
WR0A
RR0A
1
0
0
1
WR1A
RR1A
1
0
1
0
WR2
RR2A
1
0
1
1
WR3A
RR3A
1
1
0
0
WR4A
RR4A(WR4A)
1
1
0
1
WR5B
RR5A(WR5A)
1
1
1
0
WR6A
RR6A
1
1
1
1
WR7A
RR7A
With the Point High command:
0
0
0
0
WR8B
RR8B
0
0
0
1
WR9
RR9B(WR3B)
0
0
1
0
WR10B
RR10B
0
0
1
1
WR11B
RR11B(WR10B)
0
1
0
0
WR12B
RR12B
0
1
0
1
WR13B
RR13B
0
1
1
0
WR14B
RR14B(WR7’B)
0
1
1
1
WR15B
RR15B
1
0
0
0
WR8A
RR8A
1
0
0
1
WR9
RR9A(WR3A)
1
0
1
0
WR10A
RR10A
1
0
1
1
WR11A
RR11A(WR10A)
1
1
0
0
WR12A
RR12A
1
1
0
1
WR13A
RR13A
1
1
1
0
WR14A
RR14A(WR7’A)
1
1
1
1
WR15A
RR15A
2.6
RESET
The SCC may be reset by either hardware or software. A hardware reset occurs when
RD and WR are both Low, simultaneously regardless of the state of the CE input, which
is normally an illegal condition. As long as both
RD and WR are Low, the SCC recognizes
the reset condition. Once this condition is removed, however, the reset condition is as-
serted internally for an additional four to five PCLK cycles. During this time, any attempt
to access the SCC will be ignored. However a hardware reset does not clear the receive
FIFO, therefore it may be necessary to perform a few dummy reads immediately after a



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