AM8530 datasheet(65/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–13

4.6.1.3

Break Detection

A break condition is recognized when a null character (all ‘0’s) plus a Framing Error is

detected by the receiver. Upon recognizing this sequence, the BREAK/ABORT status bit

in RR0 will be set and remains set until a ‘1’ is received indicating that a break condition

is no longer present. Note that at the termination of a break, the Receive Data FIFO con-

tains a single null character, which should be read and discarded. The Framing Error bit

will not be set for this null character, but if odd parity has been selected, the Parity Error

bit will be set. Caution should be exercised if the receive data line contains a switch that

is not debounced to generate breaks. Switch bounce may cause multiple breaks, recog-

nized by the receiver to be additional characters assembled in the Receive Data FIFO. It

may also cause a Receiver Overrun condition to be latched.

4.6.1.4

Clock Selection

When an SCC channel is programmed in Asynchronous mode it may be programmed to

accept a transmit/receive clock that is 1, 16, 32, or 64 times the data rate. This is selected

by bits D7 and D6 in WR4. The clock factor chosen will be common to both the transmit-

ter and receiver.

The x1 mode in Asynchronous mode is a combination of both synchronous and asynchro-

nous transmission. The data are clocked by a common timing base, but characters are

still framed with Start and Stop bits. Because the receiver waits for one clock period after

detecting the first High-to-Low transition before beginning to assemble characters, the

data and clock must be synchronized externally. The x1 mode is the only mode in which a

data encoding method other than NRZ may be used.

In SDLC and Synchronous modes bits D7 and D6 of WR4 are ignored because the x1

clock is forced internally.

4.6.2

Transmitter Operation

In Asynchronous mode, WR6 and WR7 are not used and the Transmit Shift Register is

formatted with Start and Stop bits before data are shifted out to the transmit multiplexer at

the selected clock rate. Asynchronous data leaves the Transmit Shift Register and goes

directly to the Transmit Multiplexer. CRC generation is not supported in this mode.

4.6.2.1

Transmitter Initialization

The initialization sequence for the transmitter in Asynchronous mode is: WR4 first to se-

lect the mode, then WR3 and WR5 to select the various options. At this point the other

registers should be initialized as necessary. When all of this is complete, the transmitter

may be enabled by setting bit D3 of WR5 to ‘1’.

At this point, the transmitter is enabled and the TxD pin will remain in the marking (High)

state. When the first character is written to WR8, it is transferred to the Transmit Shift

and the selected number of Stop bits are then appended to the character. After the char-

acter has been completely sent, the next character is transferred to the Transmit Shift

the transmitter is completely empty), the All Sent status bit in RR1 (D0) will be set when

the last Stop bit reaches the TxD pin. This bit can be used by the processor as an indica-

tion that the transmitter may be safely disabled. The TxD pin then remains in the marking

state until the next character is written to WR8.

4.6.2.2

Stop Bit Selection

The SCC provides three Stop-bit options via bits D3 and D2 in WR4. The options avail-

able are one, one-and-a-half, or two stop bits per character. These two bits in WR4 select

only the number of Stop bits for the transmitter, as the receiver always checks for one

Stop bit. Note that the selected clock factor may restrict the number of Stop bits that may

be transmitted. In particular, when the clock rate and data rate are the same (i.e., x1

mode), one-and-a-half Stop bits are not allowed. If any length other than one Stop bit is

desired in the x1 mode, only two Stop bits can be used.

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