AM8530 datasheet(68/194 Pages) AMD

68 / 194 page

Data Communication Modes Functional Description

AMD

4–16

SCC Status Reg

(Existing)

14-Bit Byte Counter

Residue Bits(3)

Overrun

CRC Error

14 Bits

6 Bits

10 x 19-Bit FIFO Array

5 Bits

EOF = 1

6 Bits

RR1

2 Bits

Interface to SCC

6-Bit MUX

Bit 7

Bit 6

6 Bits

Bits 0-5

RR7

RR6

8 Bits

Byte Counter Contains 14 Bits for

a 16-Kbyte Maximum Count

FIFO Data Available Status Bit

Status Bit Set to 1

When Reading From FIFO

FIFO Overflow Status Bit

MSB of RR(7) is Set on Status FIFO

Overflow

In SDLC Mode the Following Definitions Apply

• All Sent Bypasses MUX and Equals Contents of SCC Status Register

• Parity Bits Bypasses MUX and Does the Same

• EOF is Set to 1 Whenever Reading from the FIFO

Reset on Flag Detect

Increment on Byte DET

Enable Count in SDLC

Tail Pointer

4-Bit Counter

Head Pointer

4-Bit Counter

4-Bit Comparator

Over

Equal

WR(15) Bit 2

Set Enables

Status FIFO

FIFO Enable

End of Frame Signal

Status Read Comp

RR1

Figure 4–12. 10x19-Bit Frame Status FIFO

When this FIFO is enabled, RR6 accommodates the LSB byte count from the 14-bit byte

counter and RR7 accommodates the MSB byte count along with FIFO availability and

Overflow status. Figure 4–13 shows the details of these registers including WR15.

If frame status is to be acquired from the 10x19-bit FIFO, it must be enabled and not

empty, and the registers must be read in the following order: RR7, RR6, and RR1 (read-

ing RR6 is optional). Accessing RR7 latches the FIFO Empty/Full status bit (D6 of RR7)

and steers the status multiplexer to read from the 10x19-bit FIFO array instead of from

the 8-bit Status FIFO.

Reading RR1 immediately after RR7 causes one location of the FIFO to be emptied, so

status should be read after reading the byte count; otherwise, the count will be incorrect.

If the FIFO goes empty when RR1 is read, the FIFO is disabled and the next read of RR1

will be directly from the 8-bit status FIFO, and reads from RR7 and RR6 will contain bits

that are undefined. To determine if status data is coming from the 10x19-bit FIFO or di-

rectly from the status register the user should check bit D6 of RR7. If this bit is set to ‘1’

the FIFO is not empty; if set to ‘0’ the FIFO is empty.

AM8530 Datasheet(PDF) 68 Page - Advanced Micro Devices

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