AM8530 datasheet(45/194 Pages) AMD

45 / 194 page

I/O Programming Functional Description

AMD

3–14

In External Sync Mode, the SYNC/HUNT status bit, as in Asynchronous mode, reports

the state of the

SYNC pin. If there are no other External/Status interrupts pending, then

any transition on the

SYNC pin will cause the latches to close and generate an External/

Status interrupt. However, only an odd number of transitions on

SYNC, while another Ex-

ternal/Status interrupt is pending, will close the latches and generate an External/Status

Interrupt.

3.8.2

Break/Abort

The BREAK/ABORT status bit is used in Asynchronous and SDLC modes but is always

set to ‘0’ in Synchronous modes. Both a Low-to-High and High-to-Low transition are guar-

anteed to cause the External/Status latches to close, and if the BREAK/ABORT IE bit in

WR15 is set to ‘1’, generate an External/Status interrupt regardless of whether another

External/Status interrupt is pending at the time the transitions occur. If BREAK/ABORT is

detected while the latches are closed, the status will be saved and generate an interrupt

for BREAK/ABORT detection upon issuing the Reset External/Status Interrupts. A second

interrupt is generated for End of BREAK/ABORT after issuig the next Reset External/

Status Interrupts. In the first case, the BREAK/ABORT bit will be set to ‘1’, and in the sec-

ond case to ‘0’. This will guarantee that the BREAK/ABORT sequence is detected cor-

rectly. A BREAK/ABORT occurrence will clear an End of BREAK/ABORT that is waiting

to generate an interrupt. Therefore, multiple Break/Abort sequences while the latches are

closed will generate only two interrupts, one for BREAK/ABORT detection, and one for

End of BREAK/ABORT.

In Asynchronous mode, this bit will be set to ‘1’ when a break sequence (null character

plus Framing Error) is detected (i.e., RxD is Low for more than one full character time) in

the receive data stream, and remains set for as long as ‘0’s continue to be received. It is

reset when a ‘1’ is received. Note that a single null character is left in the Receive Data

FIFO each time a break condition is terminated. This character should be read and dis-

carded.

In SDLC mode, this status bit is set to ‘1’ when an abort sequence is detected in the re-

ceive data stream and is reset when a ‘0’ is received. Note that the receiver detects an

abort pattern whether it is “in frame” or “out of frame,” so to avoid confusion, the BREAK/

ABORT IE bit in WR15 should be set to ‘1’ in the SYNC/HUNT interrupt routine when the

SYNC/HUNT status bit indicates that the receiver is “in frame” (i.e., SYNC/HUNT status

bit transitions from High-to-Low), and should be reset to ‘0’ early in the EOF interrupt rou-

tine.

3.8.3

Zero Count

The Zero Count (ZC) status bit reflects when the Baud Rate Generator counter reaches a

count of ‘0’. The ZC status bit will be set to ‘1’ when the zero count is reached and will be

reset to ‘0’ when the counter is re-loaded. The External/Status latches will close only on

the Low-to-High transition of this bit and, if the Zero Count IE bit is set in WR15, generate

an External/Status interrupt. This status bit is not latched in RR0 even though the Exter-

nal/Status latches close as a result of the transition.

If there are no other External/Status interrupt conditions pending at the time the ZC status

bit is set, an External/Status interrupt will be generated. However, if there is another Ex-

ternal/Status interrupt pending at the time ZC is set, no interrupt will be generated until

the current interrupt service is complete. If the zero count condition does not persist be-

yond the end of the current interrupt service routine no interrupt will be generated. The

interrupt service routine should check the other External/Status conditions for changes. If

none changed, the ZC was the source of interrupt. In polled applications, the IP bits in

RR3A should be checked for a status change before proceeding as in the interrupt serv-

ice routine.

Note that while the Zero Count IE bit in WR15 is reset, the ZC status bit will always read

‘0’.

AM8530 Datasheet(PDF) 45 Page - Advanced Micro Devices

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