AM8530 datasheet(79/194 Pages) AMD

79 / 194 page

Data Communication Modes Functional Description

AMD

4–27

4.8

TRANSMITTER OPERATION

In SDLC Modes, the transmitter automatically envelopes the data written to the Transmit

Buffer Register (WR8) with the flag character in WR7. Because the SCC transfers the flag

character eight bits at a time, zero-suppressed flags (i.e., where the ending zero bit of

one flag is the beginning zero bit of the succeeding flag) are not supported. The receiver,

however, can receive either zero-suppressed or fully-formed flags. While flags are trans-

mitted the zero insertion logic is inhibited.

When transmitting data in SDLC modes, note that all data passes through the zero inser-

ter, which adds an extra five bit times of delay between the Transmit Shift Register and

the Transmit Data (TxD) pin.

4.8.1

Transmitter Initialization

The initialization sequence for the transmitter in SDLC modes is: WR4 first, to select the

mode, then WR10 to modify it if necessary, WR7 and WR6 to program the flag and ad-

dress field (if used), and then WR3 and WR5 to select the various options. At this point,

the other registers should be initialized as necessary. Once all of this is complete the

transmitter will be idle with the TxD pin pulled high until the transmitter is enabled via bit

D3 in WR5. When this bit is set to ‘1’, the transmitter starts mark idling (i.e., a pattern of

all one bits are sent eight bits at a time), and continues to mark idle until the MARK/FLAG

Idle bit in WR10 (D3) is set to ‘0’. When this bit is reset to ‘0’ and the current mark idle

pattern has left the Transmit Shift Register, the transmitter will begin sending flag charac-

ters and will continue to send flag characters until a character is written to the Transmit

Buffer. During this flag idle time the CRC generator may be initialized by issuing the Re-

set Tx CRC Generator Command in WR0.

When a character is written to WR8 and the current flag character has been sent, the

transmitter starts sending data and continues to send data until an underrun condition

occurs. The Tx Buffer Empty status bit in RR0 (D2) will be set to ‘1’ each time the con-

tents of WR8 are transferred to the Transmit Shift Register. It will be reset to ‘0’ each time

the Transmit Buffer is written to, and while the CRC is being sent in SDLC and Synchro-

nous modes. If the Transmitter Interrupt Enable bit in WR1 is set to ‘1’ then the Low-to-

High transition of the Tx Buffer Empty status bit will generate an interrupt.

4.8.2

MARK/FLAG Idle Generation

The Transmitter may be programmed to either mark or flag idle when no data are being

transmitted. If the MARK/FLAG idle bit in WR10 (D3) is set to ‘1’, the transmitter will mark

idle by transmitting continuous ‘1’s; otherwise, it will flag idle by transmitting continuous

flags. The state of this bit determines the idle pattern transmitted after the closing flag of

the frame is sent and not before.

On the NMOS SCC, if the transmitter is actively mark idling, and a frame of data is ready

to be transmitted, the MARK/FLAG idle bit must be set to ‘0’ before data are written to

WR8; otherwise, the opening flag will not be sent properly. However, care must be exer-

cised in doing this because the mark idle pattern (eight ‘1’ bits) is transmitted eight bits at

a time, and all eight bits must have transferred from the Transmit Shift Register before a

flag may be loaded and sent. If data are written into the Transmit Buffer (WR8) before the

flag is loaded into the Transmit Shift Register, the data character written to WR8 will su-

persede flag transmission and the opening flag will not be transmitted.

4.8.3

Auto Flag Mode

On the CMOS SCC, if bit D0 of WR15 is set to ‘1’, and the SCC is programmed for SDLC

operation, an option is provided via bit D0 of WR7’ that eliminates this requirement. If bit

D0 of WR7’ is set to ‘1’ and a character is written to the Transmit Buffer while the Trans-

mitter is mark idling, the Mark/Flag Idle bit in WR10 need not be reset to ‘0’ in order to

have the opening flag sent because the transmitter will automatically send it before com-

mencing to send data.

In addition, as long as bit D0 of WR15 and bit D1 of WR7’ are set to ‘1’, the CRC transmit

generator will be automatically preset to the initial state programmed by bit D7 of WR10

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