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AM8530 Datasheet(PDF) 62 Page - Advanced Micro Devices |
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AM8530 Datasheet(HTML) 62 Page - Advanced Micro Devices |
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62 / 194 page ![]() Data Communication Modes Functional Description AMD 4–10 WR7 Sync Register WR6 Sync Register Transmit Data 20-Bit Transmit Shift Register Start Bit Transmit MUX & 2-Bit Delay Zero Insert (5 Bits) CRC Generator NRZI Encode Final Tx MUX TxD Internal TxD Transmit Clock To Other Channel ASYNC SYNC SDLC CRC-SDLC Internal Data Bus Figure 4–8. SCC Transmitter Table 4–1. Data Format—Five Bits or Less Bits D7 D6 D5 D4 D3 D2 D1 D0 Transmitted 1111000 D0 1 bit 111000 D1 D0 2 bits 11000 D2 D1 D0 3 bits 1000 D3 D2 D1 D0 4 bits 0 0 0 D4 D3 D2 D1 D0 5 bits The serial data stream sent by the transmitter for the six bits/character with parity case is shown below in Figure 4–9. All the unused bits are ignored by the transmit logic except in the case of five bits per character. D0 P D5 D4 D3 D2 D1 D0 P Data Flow Figure 4–9. Six Bits/Character with Parity |
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