AM8530 datasheet(88/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–36

4.10.1.5

CRC Polynomial Selection

Either of two CRC polynomials may be used in Synchronous modes. The polynomial that

will be used by both the transmitter and receiver is selected by bit D2 in WR5. If this bit is

set to ‘1’, the CRC-16 polynomial (X16+X15+X2+1) will be used; if this bit is set to ‘0’, the

CRC-CCITT polynomial (X16+X12+X5+1) will be used.

4.10.1.5.1

Rx CRC Initialization

The initial state of both transmit and receive CRC generators is controlled by bit D7 of

WR10. When this bit is set to ‘1’, both transmit and receive CRC generators will be preset

to an initial value of all ‘1’s; if this bit is set to ‘0’, they will be preset to an initial value of all

‘0’s.

The SCC presets the receive CRC generator whenever the receiver is in Hunt Mode so a

CRC reset command is not strictly necessary. However, it may be preset by issuing the

Reset CRC Checker command in WR0. The Reset CRC Checker command is necessary

in Synchronous modes if the Enter Hunt Mode command in WR3 is not issued between

received messages. Note that any action that disables the receiver in Synchronous

modes (including External Sync mode) initializes the CRC circuitry.

4.10.1.5.2

Rx CRC Enabling

If CRC is to be used on receive data the receive CRC generator must be enabled by set-

ting bit D0 of WR3 to ‘1’. If sync characters are being stripped (i.e., WR3 bit D1 set to ‘1’)

from the data stream, enabling the CRC may be done at any time before the first non-

sync character is received. If the sync strip feature is not being used, the CRC generator

must not be enabled until after the first data character has been transferred to the Re-

ceive Data FIFO. As previously mentioned, 8-bit sync characters stripped from the data

stream are automatically excluded from CRC calculation. The receive CRC generator

may be enabled and disabled as many times for a given calculation.

4.10.1.5.3

Rx CRC Character Exclusion

Being able to exclude characters from CRC calculation is possible in the SCC because

CRC calculation may be enabled and disabled on the fly. To give the processor sufficient

time to decide whether or not a particular character should be included in the CRC calcu-

lation, the SCC contains an 8-bit time delay between the Receive Shift Register and the

receive CRC generator. The logic also guarantees that the calculation will start or stop

only on a character boundary by delaying the enable or disable until the next character is

loaded into the Receive Data FIFO. To understand how this works refer to the following

explanation and Figure 4–24.

Consider a case where the SCC receives a sequence of eight bytes, called A, B, C, D, E,

F, G and H with A received first. Now suppose that A is the sync character, that CRC is to

be calculated on B, C, E, and F, and that F is the last byte of this message. Before A is

received the receiver is in Hunt mode and the CRC is disabled. When A is in the receive

shift register it is compared with the contents of WR7. Since A is the sync character, the

bit patterns match and receiver leaves Hunt mode, but character A is not transferred to

the receive data FIFO. The CRC remains disabled even though somewhere during the

next eight bit times the processor reads B and enables CRC. At the end of the eight-bit-

time, B is in the 8-bit delay and C is in the receive shift register. Character C is loaded

into the receive data FIFO and at the same time the CRC checker is enabled. During the

next eight-bit-time, the processor reads C and leaves the CRC enabled. At the end of

these eight-bit-times the SCC has calculated CRC on B, character C is the 8-bit delay

and D is in the Receive Shift register. D is then loaded into the receive data buffer and at

some point during the next eight-bit-time the processor reads D and disables CRC. At the

end of these eight-bit-times CRC has been calculated on C, character D is in the 8-bit

delay and E is in the Receive Shift register.

Now E is loaded into the receive Data FIFO and, at the same time, the CRC is disabled.

During the next eight-bit-times the processor reads E and enables the CRC. During this

time E shifts into the 8-bit delay, F enters the Receive Shift register and CRC is not being

calculated on D. After these eight-bit-times have elapsed, E is in the 8-bit delay, and F is

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