AM8530 datasheet(67/194 Pages) AMD

67 / 194 page

Data Communication Modes Functional Description

AMD

4–15

back SDLC frames by minimizing frame overruns due to CPU latencies in responding to

interrupts. The block diagram of the 10x19-bit FIFO is shown in Figure 4–12.

4.7.1.3.1

FIFO Enabling/Disabling

This Frame Status FIFO is enabled through WR15 bit D2 but only when the SCC is pro-

grammed in SDLC mode. Since each channel incorporates this FIFO, each can be en-

abled and disabled independently.

Resetting bit D2 of WR15 disables and resets the FIFO. Table 4–2 tabulates the ena-

bling/disabling of channel FIFOs. Note that the FIFO pointer logic is reset when D2 of

WR15 is reset or after a power-on reset.

When the Frame Status FIFO is disabled, the CMOS SCC is completely downward com-

patible with the NMOS SCC, and the status register contents bypass the FIFO and go

directly to the bus interface as shown in Figure 4–12.

The status of the FIFO Enable signal can be obtained by reading bits D2 of RR15 through

their respective channels. If the FIFO is enabled, this bit will be set to ‘1’; otherwise, it will

be set to ‘0’.

4.7.1.3.2

FIFO Read Operation

To facilitate the use of these FIFOs, two new registers were added. These registers, RR6

and RR7, are accessible only when bit D2 of WR15 is set to ‘1’, and the SCC is pro-

grammed in SDLC mode.

Table 4–2. Frame Status FIFO Enabling

WR15A(D2)

WR15B(D2)

Operation

Ch.A and Ch.B FIFOs disabled and reset

Ch.A and Ch.B FIFOs enabled but not independent

(resetting D2 or WR15A resets both FIFOs

simultaneously)

Ch.A and Ch.B FIFOs enabled and independent

(resetting D2 in either channel resets only pertinent

FIFO)

Ch.B FIFO enabled only

RTxC

RxD

SYNC

FLAGLAST–1

FLAGLAST

DATA0

DATA1

DATA2

Figure 4–11. Flag Detect Timing

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