AM8530 datasheet(83/194 Pages) AMD

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Data Communication Modes Functional Description

AMD

4–31

4.9.1.1

On-Loop Program Sequence

SDLC Loop mode is similar to SDLC mode except that two additional control bits are

used. They are the Loop mode bit (D1) and the Go Active on Poll bit (D4) in WR10. In

addition to these two extra control bits, there are also two status bits in RR10. They are

the On Loop bit (D1) and the Loop Sending bit (D4). Before Loop mode is selected, both

the receiver and transmitter must be completely initialized for SDLC operation. Once this

is done, Loop mode is selected by setting bit D1 of WR10 to ‘1’. At this point the SCC

connects TxD to RxD with only gate delays in the path. At the same time a flag is loaded

into the Transmit Shift register and is shifted to the end of the zero-bit inserter, ready for

transmission. The SCC will remain in this state until the Go Active On Poll bit (D4) in

WR10 is set to ‘1’. When this bit is set to ‘1’, the receiver begins looking for a sequence of

seven consecutive ‘1’s, indicating either an EOP or an idle line. When the receiver de-

tects this condition, the BREAK/ABORT status bit in RR0 is set to ‘1’ and a one-bit time

delay is inserted in the path from RxD to TxD. The On Loop bit in RR10 is also set to ‘1’

at this time, and the receiver enters Hunt Mode. The SCC cannot transmit on the loop

until a flag is received, causing the receiver to leave Hunt mode, and another EOP (bit

pattern ‘11111110’) is received. The SCC is now on the loop and capable of transmitting

on the loop. As soon as this status is recognized by the processor, the Go Active On Poll

bit in WR10 should be set to ‘1’ to prevent the SCC from transmitting on the loop without

the consent of the processor.

4.9.1.2

On-Loop Message Transmission

When a secondary station has a message to transmit and it recognizes an EOP on the

line, the first thing that it does is to change the last ‘1’ of the EOP pattern to a ‘0’ before

transmitting it. This turns the EOP into a Flag sequence. The secondary station now

places its message on the loop and terminates its message with an EOP. Any secondary

stations further down the loop with messages to transmit can then append its message to

the message of the first secondary station by the same process. All secondary stations

without messages to send merely echo the incoming messages and are prohibited from

placing messages on the loop, except upon recognizing an EOP.

4.9.1.3

On-Loop Transmit Message Programming Sequence

To transmit a message on the loop, the Go Active On Poll bit WR10 must be set to ‘1’.

Once this is done, the SCC will change the next received EOP into a Flag and begin

transmitting on the loop. At this point the processor may either write the first character to

the transmit buffer and wait for a transmit buffer empty condition or wait for the Break/

Abort and Hunt Status bits to be set to ‘1’ in RR0 and the Loop Sending bit to be set to ‘1’

in RR10 before writing the first data to the transmitter. Note that the Break/Abort and Hunt

bits in RR0 will be set to ‘1’ when the EOP is received. If the data is written immediately

after the Go Active On Poll bit has been set, the SCC will insert only one flag after the

EOP is changed into a flag. If the data is not written until after the receiver enters the

Hunt mode, flags will be transmitted until the data is written. If only one frame is to be

transmitted on the loop in response to an EOP, the processor must set the Go Active on

Poll bit to ‘0’ before the last data is written to the transmitter. In this case the transmitter

will close the frame with a single flag and then revert to the one-bit delay. The Loop Send-

ing bit in RR10 is set to ‘0’ when the closing Flag has been sent. If more than one frame

is to be transmitted, the Go Active On Poll bit should not be set to ‘0’ until the last frame is

being sent. If this bit is not set to ‘0’ before the end of a frame, the transmitter will send

Flags until either more data is written to the transmitter, or until the Go Active On Poll bit

is set to ‘0’. Note that the state of the Abort/Flag on Underrun and Mark/Flag idle bits in

WR10 are ignored by the SCC in SDLC Loop mode.

4.9.2

Going Off Loop

If SDLC Loop Mode is de-selected, the SCC is designed to exit from the loop gracefully.

When SDLC Loop mode is de-selected by writing to WR10, the SCC waits until the next

polling cycle to remove the on-bit time delay. If a polling cycle is in progress at the time

the command is written, the SCC finishes sending any message that it Figure 4–19.

Transmitter Disabling with NRZI Encoding may be transmitting, ends with an EOP, and

disconnects TxD from RxD. If no message was in progress, the SCC immediately discon-

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