AM8530 datasheet(69/194 Pages) AMD

69 / 194 page

Data Communication Modes Functional Description

AMD

4–17

Since not all status bits of RR1 are stored in the Frame Status FIFO, the All Sent, Parity,

and EOF bits bypass the FIFO and are stored in the 8-bit Status FIFO. The status bits

stored in the 10x19-bit FIFO will be the Residue, Overrun, and CRC status bits. Note that

the EOF interrupt is generated the same way as before.

4.7.1.3.3

FIFO Write Operation

When an EOF is detected, and the FIFO is enabled, the five status bits and byte-count

are loaded into the FIFO, and the FIFO pointer is incremented. If the FIFO overflows, bit

D7 of RR7 (FIFO Overflow) is set to indicate the overflow. This bit and the FIFO control

logic is reset by disabling and re-enabling the FIFO control bit (WR15 bit D2). For details

of FIFO control timing during an SDLC frame, refer to Figure 4–14.

When a packet is completely received, then a Receive Interrupt on Special Condition is

generated upon receipt of the End of Frame Flag. If the clock is temporarily stopped after

the receipt of the flag, the Frame Status FIFO may not be updated even though the inter-

rupt was generated. At least two receive clocks are needed to update the Frame Status

FIFO. The Frame Status information is not lost and will be put into the Frame Status FIFO

when the clock is enabled again.

4.7.1.3.4

14-Bit Byte Counter

The 14-bit byte counter allows for data frames of up to 16K bytes to be received. It is en-

abled when bit D2 of WR15 is set to ‘1’ and the SCC is in SDLC mode. It is reset when-

ever an SDLC flag character is received. The reset is timed so that the contents of the

byte counter are successfully written into the FIFO.

The byte counter is incremented by writes to the 8-bit receive Data FIFO. The counter

represents the number of bytes received by the SCC, rather than the number of bytes

transferred from the SCC. (These counts may differ by up to the number of bytes in the

receive data FIFO contained in the SCC.)

FOY

FDA

FIFO Data Available Status

1 = Status Reads Will Come From FIFO

0 = Status Reads Will Come From SCC

FIFO Overflow Status

1 = FIFO Overflowed During Operation

0 = Normal

RR7

Read From FIFO

LSB Byte Count

RR6

Status FIFO Enable Control Bit

1 =

WR16

FEN

Status and Byte Count Will be

Held in the Status FIFO Until Read

0 =

Status Will Not be Held (SCC)t

(Emulation Mode)

* =

No Change From NMOS SCC DFN

10216A-013A

Figure 4–13. Frame Status FIFO Registers

AM8530 Datasheet(PDF) 69 Page - Advanced Micro Devices

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