AM8530 datasheet(16/194 Pages) AMD

16 / 194 page

General Information

AMD

1–8

1.5

PIN DESCRIPTIONS

Figure 1–4 designates the pin locations and signal names for the 40- and 44-pin SCC

versions.

1.5.1

System Interface Pin Descriptions

A/B — Channel A/Channel B Select (input, Channel A active High)

This signal selects the channel in which the Read or Write operation occurs and must be

valid prior to the read or write strobe.

CE — Chip Enable (input, active Low)

This signal selects the SCC for operation. It must remain active throughout the bus

transaction.

D0–D7 — Data Lines (bidirectional, 3-state)

These I/O lines carry data or control information to and from the SCC.

D/C — Data/Control (input, data active High)

This signal defines the type of information transfer performed by the SCC: data or control.

The state of this signal must be valid prior to the read or write strobe.

RD — Read (input, active Low)

This signal indicates a Read operation and, when the SCC is selected, enables the SCC

bus drivers. During the interrupt acknowledge cycle, this signal gates the interrupt vector

onto the bus provided that the SCC is the highest priority device requesting an interrupt.

WR — Write (input, active Low)

When the SCC is selected, this signal indicates a Write operation. On the NMOS

Am8530H data must be valid prior to the rising edge of write strobe. The Am85C30 does

not share this requirement. The coincidence of

RD and WR is interpreted as a Reset.

IEI* — Interrupt Enable In (input, active High)

IEI is used with IEO to form an interrupt daisy chain when there is more than one inter-

rupt-driven device. A High on IEI indicates that no other higher priority device has an In-

terrupt Under Service (IUS) or is requesting an interrupt.

IEO — Interrupt Enable Out (output, active High)

IEO is High only if IEI is High and the CPU is not servicing an SCC or SCC interrupt or

the controller is not requesting an interrupt (interrupt acknowledge cycle only). IEO is con-

nected to the next lower priority device’s IEI input and thus inhibits interrupts from lower

priority devices.

INTACK* — Interrupt Acknowledge (input, active Low)

This signal indicates an active interrupt acknowledge cycle. During this cycle, the interrupt

daisy chain settles. When

RD becomes active, the SCC places an interrupt vector on the

data bus (if IEI is High).

INTACK is latched by the rising edge of PCLK.

INT — Interrupt Request (output, open-drain, active Low)

This signal is activated when the SCC is requesting an interrupt.

Note:

*Pull-up resistors are needed on

INTACK and IEI inputs if they are not driven by the

system and for the

INT output. If INTACK or IEI are left floating, the Am85C30 will

malfunction.

INT is an open drain output and must be pulled up to keep a logical high

level.

AM8530 Datasheet(PDF) 16 Page - Advanced Micro Devices

AM8530 Datasheet(HTML) 16 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL