AM8530 datasheet(31/194 Pages) AMD

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System Interface

AMD

2–13

hardware reset to ensure that the FIFO is completely flushed before the new data can be

received reliably.

The SCC has three software resets encoded into command bits in WR9. There are two

channel resets, which affect only one channel in the device and some of the bits in the

write registers. The third command forces the same result as a hardware reset. As in the

case of a hardware reset, the SCC stretches the reset signal an additional four to five

PCLK cycles beyond the ordinary valid access recovery time. When the SCC is first pow-

ered up, performing a read with the D/

C pin held Low will guarantee that the pointers are

reset to ‘0’; then a reset command can be issued by selecting WR9 and writing to it. The

bits in WR9 may be written at the same time as the reset command because these bits

are affected only by a hardware reset. The reset values of the various registers are

shown in Figure 2–4.

0 1

0 0

0 1

0 0

Hardware Reset

Channel Reset

WR0

WR1

WR2

WR3

WR4

WR5

WR6

WR7

WR9

WR10

WR11

WR12

WR13

WR14

WR15

RR0

RR1

RR3

RR10

Figure 2–4. SCC Register Reset Values

AM8530 Datasheet(PDF) 31 Page - Advanced Micro Devices

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