AM8530 datasheet(38/194 Pages) AMD

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I/O Programming Functional Description

AMD

3–7

IEI

IEO

INT

INTACK

IEI

IEO

INT

INTACK

IEI

IEO

INT

INTACK

IEI

IEO

INT

INTACK

5 V

SCC

Figure 3–3. External Daisy Chain

INTERRUPT VECTOR

RECEIVER CHANNEL A

INTERRUPT

IEI

INTACK

INT

IEO

TRANSMIT CHANNEL A

INTERRUPT

IEI

INTACK

INT

IEO

EXTERNAL/STATUS

CHANNEL B INTERRUPT

IEI

INTACK

INT IEO

INTACK

IUS

DLC

MIE

VIS

Figure 3–4. Internal Daisy Chain

Each SCC on the daisy chain uses PCLK to latch the state of the Interrupt Acknowledge

signal,

INTACK. If a Low INTACK is latched, then the present cycle is an interrupt ac-

knowledge cycle and the daisy chain determines which interrupt source is being acknowl-

edged in the following way. Any interrupt source that has an interrupt pending and is not

masked from the chain will hold its IEO line low. Similarly, sources that are currently un-

der service will also hold their IEO lines low.

All other interrupt sources make IEO follow IEI. The result is that only the highest priority,

unmasked source with an interrupt pending will have a high IEI input. This SCC will be

allowed to transfer its vector to the system bus when the

RD strobe is issued during the

interrupt acknowledge cycle.

To ensure that the daisy chain has settled by the time

RD gates the vector onto the bus,

the SCC requires a delay between falling edge of

INTACK and the falling edge of RD (AC

timing parameter #38, TdlAi(RD)). The internal daisy chain may be controlled by the MIE

bit in WR9. This bit, when reset, has the same effect as pulling the IEI Low, thus disabling

all interrupt requests.

AM8530 Datasheet(PDF) 38 Page - Advanced Micro Devices

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