AM8530 datasheet(57/194 Pages) AMD

57 / 194 page

Data Communication Modes Functional Description

AMD

4–5

and provides the mechanism by which character synchronization is established at a re-

ceiver. Since data between flags may contain the flag pattern, the sequence of six con-

secutive one bits is prevented from occurring through a process called zero-bit insertion,

in which the transmitter inserts a zero bit after any five consecutive one bits. Likewise, the

receiver deletes any zero bit that follows five consecutive one bits in the bit stream be-

tween the opening and closing flag of a frame.

SYNC

DATA

CRC

Figure 4–2. MONOSYNC Format

SYN

HEADER

TEXT

EXT

ETB

BCC

SYN

SOH

STX

DIRECTION OF SERIAL DATA FLOW

BCC = Block Checking Calculation

Figure 4–3. BISYNC Format

BEGINNING

FLAG

01111110

8 BITS

ADDRESS

8 BITS

FRAME

CHECK

16 BITS

CONTROL

8 BITS

INFORMATION

ANY NUMBER

OF BITS

FRAME

ENDING

FLAG

01111110

8 BITS

Figure 4–4. SDLC/HDLC Frame Format

The Frame Check Sequence (FCS) is 16 bits long and contains the generated CRC for

the frame. All data transmitted between the opening and closing flags (excluding inserted

zeros) are included in the CRC calculation. The generator polynomial used in SDLC is the

CCITT polynomial, X16 + X12 + X5 + 1.

Since the information field may contain any number of bits and not necessarily an integral

number of 8-bit characters, the end of a frame is determined by counting back 16 bits

from the closing flag of a frame.

In the sections that follow, the term “Synchronous mode(s)” will be used to refer to either

BISYNC and/or MONOSYNC modes, and SDLC mode will be used when referring to nor-

mal SDLC operation. SDLC Loop mode will be referred to as either Loop mode or SDLC

Loop mode.

4.3

MODE SELECTION

The mode that an SCC channel operates in is selected by programming WR4 as shown

below. Note that the ‘x’s indicate a don’t care condition (i.e., bit setting are ignored by

SCC) and ‘?’s indicate programmable settings.

Note that bits D7 and D6 of WR4 are ignored in SDLC and Synchronous modes because

the x1 clock is forced internally.

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