AM8530 datasheet(155/194 Pages) AMD

155 / 194 page

SCC Application Notes

AMD

7–6

Table 7–2. SCC Initialization Order

Part 1. Modes and Constants

WR9

1100000

Hardware Reset

WR4

XXXXXXXX Tx/Rx con, Aysnc or Sync Mode

WR1

0XX00X00 Select W/REQ (opt)

WR2

XXXXXXXX Program Interrupt Vector (opt)

WR3

XXXXXXX0 Select Rx Control

WR5

XXXX0XXX Select Tx Control

WR6

XXXXXXXX Program sync character (opt)

WR7

XXXXXXXX Program sync character (opt)

WR9

000X0XXX Select Interrupt Control

WR10

XXXXXXXX Miscellaneous Control (opt)

WR11

XXXXXXXX Clock Control

WR12

XXXXXXXX Time constant lower byte (opt)

WR13

XXXXXXXX Time constant upper byte (opt)

WR14

XXXXXXX0 Miscellaneous Control

WR14

XXXSSSSSCommands (opt)

Part 2. Enables

WR14

000SSSS1 Baud Rate Enable

WR3

SSSSSSS1 Rx Enable

WR5

SSSS1SSS Tx Enable

WR0

10000000

Reset Tx CRG (opt)

WR1

XSS00S00 DMA Enable (opt)

Part 3. Interrupt Status

WR15

XXXXXXXX Enable External/Status

WR0

00010000

Reset External Status

WR0

00010000

Reset External Status twice

WR1

SSSXXSXX Enable Rx, Tx and Ext/Status

WR9

000SXSSS Enable Master Interrupt Enable

1 = Set to one

X = User defined

0 = Reset to zero

S = Same as previously

prog.

7.1.1.3

Initialization Table Generation

Table 7–1 as shown previously, is a worksheet for the initialization of the SCC. All the bits

that must be programmed as either a ‘0’ or a ‘1’ are already filled in; the remaining bits

are left blank and are to be programmed by the user according to the desired mode of

operation. The binary value can then be converted to a hexadecimal number and placed

in the table, following the Write register notation in the column labeled “HEX.” A Program

Initialization Table is produced when this worksheet is completed.

7.1.1.4

Reset Conditions

Prior to initialization, the SCC should be reset by either hardware or software. A hardware

reset can be accomplished by simultaneously grounding RD and WR. A software reset

can be executed by writing a C0H to Write Register 9. After one channel has been initial-

ized, a channel reset should be used in place of the hardware reset in the initialization.

The state of the SCC registers, after reset, is shown in Table 7–3. Before writing to the

SCC, a read should be performed to guarantee the internal logic is pointing to Register 0.

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