AS3515_08 datasheet(38/67 Pages) AMSCO

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AS3515 V15

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 3.1

- 66

CVDD / DCDC3 Register (21h)

Table 38 CVDD / DCDC3 Register

Bit

Name

Description

CP_SW

charge pump / length regulator switch margin reduction

0: margin set to 200/300 mV

1: margin reduced to 150/225 mV (automatic switching to length regulator is done “later”,

at a lower input voltage)

CP_on

0: normal operation

1: keeps Mode 3 charge pump always on

Please note that bit 2 = “0”, overrides bit 6.

LREG_CPnot

write:

For testing purpose only, must be set to 0h

read:

0: CP is working

1: LREG is working

4,3

DCDC3p

DCDC3 Vout programminig

00: 3.6V

01: 3.2V

10: 3.1V

11: 3.0V

LREG_off

0: keeps Mode 2 length regulator always on

1: normal operation

0,1

CVDDp1

CVDD trimming:

00: Vnom

01: Vnom –50mV

10: Vnom –100mV

11: Vnom – 150mV

The register is R/W; default value is 20h

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