DMC73C167 datasheet(59/90 Pages) DAEWOO

59 / 90 page

8Bit Single Chip Microcontroller

DMC73C167

Table 5-36. P54 0136h SADDR I2C Slave Address

Bit

Not Used

7-bit Slave Address

Bit 7

Not used.

Bit 6-0

7-bit Slave Address Register (READ/WRITE).

The Slave address register is programmable. This register must be set

with the appropriate value before the slave hardware logic is enabled,

that is before setting the ENABLE bit of SCTL.

Table 5-37. P55 0137h SDATA I2C Slave Data

Bit

Slave Receive Data

Slave Transmit Data

Bit 7-0

Slave Receive/Transmit Data (READ/WRITE).

The CPU can read or write parallel 8-bit data. During data transfer from/

to the I2C, data is shifted bit by bit. The receiving data will be read when

INT5_2F=1, after which the INT5_2F flag should be cleared. The transmitting

data will be written when INT5_2F=1, after which the INT5_2F flag should

be cleared.

5.7.2.2 Timing of Slave Mode Operations

5.7.2.2.1 Slave Receiver Mode

If the slave receives its slave address from the master, the contents of the P56 register

will be set to SEL=1/SDIR=0/GCALL=0/INT5_2F=0. If one byte of data is received,

the INT5_2F flag will be set, and the interrupt will occur. At that time the contents of

the P56 register will be set to SEL=1/SDIR=0/GCALL=0/INT5_2F=1. After that,

the INT5_2F flag will be set every time one byte of data is received.

This waveform shows the address cycle and the transfer of one byte of data during the

master transmitter mode (slave receiver mode). At the seventh SCL high, if the slave

address matches, the SEL bit will be set. At the eighth SCL high, the SDIR bit will be

set to zero, and after the eighth SCL falling, the slave will generate ACK on the SDA

line. On receipt of each byte of data from the master, the slave interrupt (INT5_2F)

is generated.

£Ä£Á£Å£×£Ï£Ï

DAEWOO ELECTRONICS CO., LTD.

DMC73C167 Datasheet(PDF) 59 Page - Daewoo Semiconductor