DMC73C167 datasheet(40/90 Pages) DAEWOO

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8Bit Single Chip Microcontroller

DMC73C167

5.5.1.3 Event Counter Mode (EC)

When Timer 1 is in event counter mode, port A1 is the clock source for Timer 1.

The maximum clock frequency on A1 at the event counter mode must not be greater than

Fosc/4. The minimum pulse width must not be less than 2/Fosc. Each positive pulse

Transition decrements the counter chain.

5.5.1.4 Timer 1 Interrupt Period

The period of the timer INT2_0 interrupt can be calculated as follows.

tINT = tCLK x (PL + 1) x (TL +1)

where :

tINT = period of timer interrupt

tCLK = 4/Fosc. for the internal real-time clock mode or the period of the input

clock source at the external EC mode

PL = Prescaler latch value (00h-1Fh : 5-bit)

TL = Decrementer reload value (0000h-FFFFh : 16-bit)

Example

min : 1us

(Fosc : 4MHz) max : 2.097 sec

5.5.1.5 Capture Latch

The current value of the decrementer is stored in the capture latch register at the active

edge of Port A3. The active edge is determined by the INT-1 EDGE bit of the IOCTL2 (P2.1)

5.5.1.6 Timer Output Function

A timer output function exists on Timer 1 that allows the B0 output to be toggled every timer

decrements through zero. This function is enabled by the T1OUT bit of the timer control

changed by writing to the B port data register. Writing to the timer's START bit will reload

and start the timer but will not toggle the output. The output will toggle only when the timer

decrements through zero. The timer output feature is independent INT2_0 and therefore

will operate whether or not INT2_0 is enabled.

Whenever the T1OUT bit is returned to 0, B0 will become the normal output port. The value in

the B0 data register will be the last value output by the timer output function, and the CPU

can control the B0 data.

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