DMC73C167 datasheet(35/90 Pages) DAEWOO

35 / 90 page

8Bit Single Chip Microcontroller

DMC73C167

The interrupt flag (INTn-mF) is set to 1 by the INTn_m input. The INTnF flag becomes active

when INTnE is 1, then INTn occurs if the interrupt enable bit (I bit) of the status register is

set to 1.

Figure 5-2. External Interrupt Logic (n = 1, 3 or 5 ; m = 0)

To conserve the low power requirement, one low-power mode - the HALT MODE - is provided.

It is invoked by executing an IDLE instruction. An external interrupt will release the device from

the low-power mode depending on whether it is in the HALTmode. When an external interrupt

is first asserted, its level is gated into an interrupt flag. In order for an interrupt signal to be

detected, the pulse duration must be a minimum of five internal clock cycles.

The INTn Enable bit is used separately to individually mask interrupt levels, and must be set 1

for the interrupt to be recognized.

As Previously stated, all interrupt control bits are implemented in the IOCTL0, IOCTL1, IOCTL2,

IOCTL3, and IOCTL4 registers in the peripheral file. I/O instructions may simply read from and

write to each INTn Enable bit. By the INTn input, the interrupt flag is set to 1 at the falling or

rising edge and becomes active when an interrupt is enabled.The interrupt service routine is

executed after the currently executing instruction is completed. Once the interrupt has been

acknowledged by the CPU, the CPU then pushes the contents of the status register and the

program counter (MSB and LSB), respectively, onto the stack and makes zero the status

counter, and the interrupt service routine is executed. The external interrupts, INT1, INT3_0,

and INT5_0, have Schmitt-trigger inputs and can be used as zero-cross detectors.

Because the pins can be used as both external interrupt pins and general-purpose I/O pins,

the following points should be noted :

Write

Read

Enable Latch

Write

Read

Enable Latch

InmCLR

EXTINTn

(SCHIMITT)

SENSnm

InmFLG

Read

InmENA

INTnE

INTn

Happen

Interrupt Enable

(ST : Status Register)

Read

INTnF

INTn Enable

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