DMC73C167 datasheet(44/90 Pages) DAEWOO

44 / 90 page

8Bit Single Chip Microcontroller

DMC73C167

5.5.2.4 Timer 2 and Timer 3 Interrupt Period

The Period of the timer interrupts INT2_1 and INT3_1 can be calculated as follows.

tINT = tCLK x (PL + 1) x (TL +1)

where :

tINT = period of timer interrupt

tCLK = 4/Fosc. for the internal real-time clock mode or the period of the input

clock source at the external EC mode

PL = Prescaler latch value (0h-3h : 2bit)

TL = Decrementer reload value (00h-FFh : 8bit)

- In case of not cascade (INT2_1 and INT3_1)

Example :

min : 1us

(CPUCLK : 4MHz)

max : 1.024ms

- In case of Timer 2 and Timer 3 cascade (INT3_1)

Example :

min : 1us

(CPUCLK : 4MHz)

max : 1.048sec.

5.5.2.5 Capture Latch

The current value of the decrementer is stored in the capture latch register at the active edge

of port A4 (INT3_0) for Timer 2 and port A5 (INT5_0) for Timer 3. The active edge is determined

by the INT3_0 EDGE and INT5_0 EDGE bits of the IOCTL2 register (P2). The capture latch

5.5.2.6 Timer Output Function

A timer output function exists on Timer 3 that allows the B1 output to be toggled every time

the timer decrements through zero. This function is enabled by the T3OUT bit of the T2CTL

by writing to the B port data register. Writing to the timer's START bit will reload and start the

timer but will not toggle the output. The output will toggle only when the timer decrements

through zero. The timer output feature is independent of INT3_1 and therefore will operate

whether INT3_1 enabled or not.

Whenever the T3OUT bit is returned to 0, B1 will become the normal output port. The value

in the B1 data register will be the last value output by the timer output function, and the CPU

can control the B1 data.

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