DMC73C167 datasheet(22/90 Pages) DAEWOO

22 / 90 page

8Bit Single Chip Microcontroller

DMC73C167

4.8 Interrupt and Reset Priorities

The DMC73C167 has priority servicing of five interrupt levels and RESET. These levels

are defined as shown in Table 4-3. The TRAP instructions branch to two-byte location in a

reserved section of memory called the TRAP vector table. As shown in Figure 4-5. each trap

location stores a 16-bit address that references either the reset function (TRAP0), one of the

five interrupt service routines (TRAP1-INT1, TRAP2-INT2, TRAP3-INT3, TRAP4-INT4, TRAP5-

INT5), or a subroutine (TRAP6-23). Once the interrupt has been acknowledged, the CPU then

pushes the contents of the status register and the program counter (MSB and LSB) onto the

stack and zeros the status register, including the global interrupt Enable (I) bit.

The CPU reads an interrupt code from the interrupt logic and branches to the address

contained in the corresponding interrupt vector location in memory. The interrupt service routine

can explicitly enable nested interrupts by executing the EINT instruction to directly set the I bit

in the status register to 1, thus permitting routine is completed, it returns to the previous interrupt

service routine by executing the RETI instruction.

Table 4-3. Interrupt and Reset Priorities

Level

Name

Source

Trigger Factor

Vector

MSB

LSB

/Reset

External

Active Low

FFFEh

FFFFh

INT1

External

Falling/Rising

FFFCh

FFFDh

INT2_0

Timer 1

Timer 1 underflow

FFFAh

FFFBh

INT2_1

Timer 2

Timer 2 underflow

INT3_0

External

Falling/Rising

FFF8h

FFF9h

INT3_1

Timer 3

Timer3 underflow

INT4

OSD

OSD enable

FFF6h

FFF7h

INT5_0

External

Falling/Rising

FFF4h

FFF5h

INT5_1

12C master

Data ready from slave

INT5_2

12C slave

Slace address selected

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