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DMC73C167 Datasheet(PDF) 49 Page - Daewoo Semiconductor |
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DMC73C167 Datasheet(HTML) 49 Page - Daewoo Semiconductor |
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49 / 90 page  49 8Bit Single Chip Microcontroller DMC73C167 5.7 I2C The DMC73C167 contains a I2C master/slave transceiver hardware interface. The I2C bus is a serial communication system, and requires serial data SDA and an associated data clock SCL. As the chip is fully programmable by software, it can be used for master mode, slave mode, and/or multi-master mode operations. Both the SCL and SDA pins are input and open-drain output pins. For the DMC73C167, the slave address is as follows. A6 A5 A4 A3 A2 A1 A0 R/W 0 1 1 0 1 A1 A0 The hardware (pin) programmable address bits are A1 and A0. Figure 5-11 I2C Block Datagram Note : SDA, SCL = Open drain output, Schmitt input I2C Clock=Min 1952Hz-Max 71.86KHz (CPU CLK : 4MHz) Master Duty High Counter Duty Low Counter SCL I2C Clock I2C Clock for Slave Master Transmit Data Receive Data SDA I2C Data Digital Filter Digital Filter Slave Transmit Data Receive Data Slave Address £Ä£Á£Å£×£Ï£Ï DAEWOO ELECTRONICS CO., LTD. |
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