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DMC73C167 Datasheet(PDF) 43 Page - Daewoo Semiconductor |
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DMC73C167 Datasheet(HTML) 43 Page - Daewoo Semiconductor |
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43 / 90 page ![]() 43 8Bit Single Chip Microcontroller DMC73C167 Bit 7 START. Timer 2 Start/stop Control 0 = Stops Timer 2. 1 = Starts Timer 2. Table 5-24. P26 011Ah T3DATA Timer 3 Data Bit 7 6 5 4 3 2 1 0 R 8-bit Timer Decrementer Value W 8-bit Timer Reload Register Table 5-25. P27 011Bh T3CTL1 Timer 3 Control Bit 7 6 5 4 3 2 1 0 R Capture Latch Value W START T3SRC Not Used Prescaler Reload Read : Provides the value of the capture register which contains the latched value of the decrementer register when INT3_0 was most recently activated. Write : Timer 3 control as below. Bits 0, 1 Rescaler Road. Reload the 2-bit Prescaler Reload Register. Bits 2-5 Not used. Bit 6 T3SRC. Select Timer 3 Clock Source. 0 = Internal clock (Fosc/4). 1 = Timer 2 underflow (Cascade mode) Bit 7 START. Timer 3 Start/stop Control 0 = Stops Timer 3. 1 = Starts Timer 3. 5.5.2.2 Real-Time Clock (RTC) In real-time clock mode, the internal Fosc/4 is the decrementer clock source. Each positive pulse transition of the Fosc/4 period signal decrements the counter chain. 5.5.2.3 Event Counter (EC) When Timer 2 is in event counter mode, port A2 (ECI2) is the decrementer clock source for Timer 2. The maximum clock frequency on A2 in event counter mode must not be greater than Fosc/4. The minimum pulse duration must not be less than 2/Fosc. Each positive pulse transition decrements the counter chain. It is not possible for Timer 3 to be in event counter mode. £Ä£Á£Å£×£Ï£Ï DAEWOO ELECTRONICS CO., LTD. |
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