DMC73C167 datasheet(29/90 Pages) DAEWOO

29 / 90 page

8Bit Single Chip Microcontroller

DMC73C167

(IOCTL3), and P4 (IOCTL4) of the peripheral file. The individual interrupt mask and resets

are controlled through these registers. The interrupt sources may also be individually

tested by reading the interrupt flags or corresponding input ports. The INTn FLAG values

are independent of the INTn ENABLE values. Writing a 1 to the INTn CLEAR bit will clear

the corresponding INTn FLAG, but writing 0 to the INTn CLEAR bit has no effect on the bit.

For INTn to be recognized by the CPU, three conditions must be met.

1) A 1 must be written to the INTn ENABLE bit in the IOCTL0, IOCTL1, IOCTL3, or IOCTL4

2) The global INTERRUPT ENABLE bit, that is bit 4 in the status register, must be set to 1

by the EINT instruction.

3) INTn must be the highest priority interrupt asserted within an instruction boundary.

Table 5-11. Interrupt Control Registers

P0 0100h IOCTL0 Interrupt Control 0

Bit

INT3F

INT3E

INT2F

INT2E

INT1F

INT1E

INT1CLR

P0 0101h IOCTL1 Interrupt Control 1

Bit

Not used

INT5F

INT5E

INT4F

INT4E

INT4CLR

P0 0102h IOCTL2 Interrupt Control 2

Bit

Not used

INT3_0

INT1

INT5_0

EDGE

P0 0103h IOCTL3 Interrupt Control 3

Bit

INT3_1F

INT3_1E

INT3_0F

INT3_0E

INT2_1F

INT2_1E

INT2_0F

INT2_0E

INT3_1C

INT3_0C

INT2_1C

INT2_0C

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