AFE4403 datasheet(45/97 Pages) TI

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ADC Clock

ADC Convert

LED2 Data

ADC Output Rate

PRF Samples per Second

ADC

Ambient

(LED2) Data

LED1 Data

Ambient

(LED1) Data

Rx Digital

Averager

22-Bits

LED2 Data

LED2_Ambient Data

LED1 Data

LED1_Ambient Data

ADC Reset

ADC

AFE4403

www.ti.com

SBAS650B – MAY 2014 – REVISED JULY 2014

8.4 Device Functional Modes

8.4.1 ADC Operation and Averaging Module

After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 49). Each ADC

conversion takes 50 µs.

The ADC operates with averaging. The averaging module averages multiple ADC samples and reduces noise to

improve dynamic range. Figure 62 shows a diagram of the averaging module. The ADC output is a 22-bit code

that is obtained by discarding the two MSBs of the 24-bit registers (for example the register with address 2Ah),

as shown in Figure 63.

Figure 62. Averaging Module

Figure 63. 22-Bit Word

Ignore

22-Bit ADC Code, MSB to LSB

Table 3 shows the mapping of the input voltage to the ADC to its output code.

Table 3. ADC Input Voltage Mapping

DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT

22-BIT ADC OUTPUT CODE

–1.2 V

1000000000000000000000

(–1.2 / 221) V

1111111111111111111111

0000000000000000000000

(1.2 / 221) V

0000000000000000000001

1.2 V

0111111111111111111111

The data format is binary twos complement format, MSB-first. Because the TIA has a full-scale range of ±1 V, TI

recommends that the input to the ADC does not exceed ±1 V, which is approximately 80% of its full-scale.

In cases where having the processor read the data as a 24-bit word instead of a 22-bit word is more convenient,

the entire register can be mapped to the input level as shown in Figure 64.

Figure 64. 24-Bit Word

24-Bit ADC Code, MSB to LSB

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